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register inferred by blocking assignment and races in verilog

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shikharmakkar

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I am new to verilog and have a doubt concerning the race conditions in the following code which is taken from FPGA Prototyping by Veriloog Examples by Pong P. Chu. The code is:

Code Verilog - [expand]
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always @(posedge clk)
  a = b;
 
 
always @(posedge clk)
  b = a;



This will infer races depending on which always block gets executed first. But always blocks should get executed in parallel. Correct me if I am wrong. I know there is blocking assignment but how does it affect the first statement of the block, which is the always statement?
The second code using the non-blocking assignment is:-

Code Verilog - [expand]
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always @(posedge clk)
begin //b(entry) = b
  a <= b; //a(exit) = b(entry)
end //a = a(exit)
 
 
always @(posedge clk)
begin //a(entry) = a
  b <= a; //b(exit) = a(entry)
end //b = b(exit)


This will work fine according to the book but I couldn't understand why? Is it because the always blocks are executed in parallel in this case because of non-blocking assignment?
 

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The issue is not the hardware, it will run in parallel it is with how a simulator (which is running a single thread of software) has to emulate the real world parallel events.

In the case of the first blocking version the always blocks are triggered on the positive edge of the clock. A simulator must then schedule the events in the always blocks and can do so in any order. Blocking statements must complete before any other events scheduled at the same time can be evaluated, therefore the events a=b and b=a could either leave the results as both a & b being either a or b depending on which assignment gets evaluated first. This is one of the reasons you should not use blocking assignments in a edge sensitive always block (i.e. to describe a D-FF).

In the second case D-FFs are described correctly as the event scheduling for non-blocking assignments are done after the Right-Hand-Side (RHS) is evaluated for all non-blocking events. The evaluated RHS is then assigned to the LHS. So specifically in the example the simulator first evaluates the RHS so a<=b (save b) and b<=a (save a). then when the assignment occurs the saved b is assigned to a and the saved a gets assigned to b.

If you want the specific details refer to the LRM or a book/paper that explains Verilog's event scheduling.
 

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