Regards to vhdl flipflop

[jianhuachews]

hi guys, i want to obtain 2outputs ff outputs from the same input driven in. Everytime i press on "ff_return", the ff begins. Below is my program. I tried compiling it but it showed an error in modelsim. Can anyone guide and enlighten me? Thanks in advance.

# ** Error: C:\Modeltech_pe_edu_10.0a\examples\test_flipflop.vhd(23): Cannot read output "q".

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all;

entity flipflop is port(
     ff_keyin: in std_logic_vector(15 downto 0);
     ff_clk, ff_return, ff_rst: in std_logic; 
     q, qbar: out std_logic_vector(15 downto 0));  -- q is the first ff output, while qbar is the second ff output from q.
end flipflop; 
architecture behavioral OF flipflop is
signal ff_return_int, done: std_logic;
begin 
process(ff_clk)
begin
  if(ff_rst='1') then
     qbar <= (others => '0');
     q <= (others => '0');
  elsif(ff_clk'event and ff_clk='1') then
    if(ff_return='1') then
     q <= not ff_keyin; 
     ff_return_int <= '1';
    elsif(ff_return_int='1') then
      qbar <= not q;
   end if;
  end if;
 end process; 
end behavioral;

 

[TrickyDicky]

you need a temporary signal internally as you cannot read output ports, so this line is illegal:

qbar <= q;

just create something like this:

signal q_temp : std_logic_vector(15 downto 0);

q <= q_temp;
qbar <= not q_temp;

 

[FvM]

The other option is to define q as buffer instead of output.

Apart from this problem, there are details in your code, that don't look well considered. ff_return_int is only set but never reset.

 

[jianhuachews]

oh yes thanks a lot tricky! i should assign it to a temp signal instead i totally forgot about it.
hi FvM, i'm not familiar with buffer... so yea. Thanks for helping, i'd my ff_return_int reset after some modifications. Thanks for the guide!

Anyway i've kinda modified my program. can anyone tell me if it make sense to my objective?

objective

i want to obtain 2outputs ff outputs from the same input driven in. Everytime i press on "ff_return", the ff begins.

i realised if i ff it twice it would go back to the original data, how stupid am i.. below is the modified program! I'd it simulated and it looks fine... I think.

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all;

entity flipflop is port(
     ff_keyin: in std_logic_vector(15 downto 0);
     ff_clk, ff_return, ff_rst: in std_logic; 
     firstq, secondq: out std_logic_vector(15 downto 0)); 
end flipflop; 
architecture behavioral OF flipflop is
signal ff_return_int: std_logic;
signal firstq_s, secondq_s: std_logic_vector(15 downto 0);
begin 
process(ff_clk)
begin
  if(ff_rst='1') then
        firstq_s <= (others => '0');
        secondq_s <= (others => '0');
        ff_return_int<='0';
  elsif(ff_clk'event and ff_clk='1') then
    if(ff_return='1') then
        firstq_s <= ff_keyin; 
        ff_return_int <= '1';
    else
        ff_return_int <= '0';
    end if;
    
      if(ff_return_int='1') then
          if(ff_return='1') then
         secondq_s <= not ff_keyin;
         ff_return_int <= '0';
      end if;
   end if;
  end if;
 end process; 
 firstq<=firstq_s;
 secondq<=secondq_s;
end behavioral;

---------- Post added at 22:18 ---------- Previous post was at 21:54 ----------

hi guys i have another question too. how do i go about adding data? is there any operand in hdl that allows something like a + b; ?
I actually did something like this but sure enough, the compile failed me.

process(add)
begin
       if (add='1') then
         firstq_s(15 downto 12) + secondq_s(15 downto 12);
         firstq_s(11 downto 8) + secondq_s(11 downto 8);
         firstq_s(7 downto 4) + secondq_s(7 downto 4);
         firstq_s(3 downto 0) + secondq_s(3 downto 0);
       end if;
end process;

 

[TrickyDicky]

you cannot add two std_logic_vectors, because they are not numbers, just a load of bits. Also, you need to assign the addition to something else

you need to convert them to signed or unsigned types, which uses the numeric_std package.

You can get away with something like this:

use ieee.numeric_std.all;

output <= std_logic_vector( unsigned(firstq_s(15 downto 12)) + unsigned( secondq_s(15 downto 12) ) );

 

[treqer]

fpga developer fundamental error. be aware that in the fpga is composed of flip-flop and not violate the logic of their management, but do not create in hdl these flip-flops and talk about them as flip-flop.

 

[jianhuachews]

Hi guys, can anyone help me with this? Modelsim gave me an error "Cannot resolve slice name as type ieee.std_logic_1164.STD_LOGIC."
it's urgent please help!

process(add)
begin
       if (add='1') then
        add_op_s (15 downto 0) <= firstq_s + secondq_s;   --both firstq_s and secondq_s are 16 bits each, while add_op_s has 17 bits.
        overflow_s <= add_op_s(16 downto 15);                --most priority bit from add_op_s should go to overflow_s
       end if;
end process;
add_op<= add_op_s(15 downto 0);
overflow<= overflow_s;
end behavioral;

---------- Post added at 19:13 ---------- Previous post was at 19:10 ----------

It was ok earlier when i did it like this, but i forgot abt the overflow (if any) thats why i modified my program to the above one.

process(add)
begin
       if (add='1') then
        add_op_s  <= firstq_s + secondq_s;    -- all signals here are 16 bits and it works here.
       end if;
end process;
add_op<= add_op_s;
end behavioral;

 

[FvM]

overflow_s <= add_op_s(16 downto 15) is assigning two bits to one. How should this work? To combine two bits into one, some kind of logical operation has to be performed.

 

[jianhuachews]

omg sorry my bad! it's done now! but when i simulate it with tb it didn't perform the addition correctly! Can you take a look at it? I've attached a waveform. the expected output for overflow_s and add_op_s is supposed to be '1' and " 1111 1111 1111 1111" after adding firstq_s and secondq_s.

 

[FvM]

The simulation result is correct for this expression

add_op_s (15 downto 0) <= firstq_s + secondq_s;

Don't know what you expect otherwise?

 

[jianhuachews]

yes the expression is right! but the output result wasn't. the waveform shows that the output add_op_s and secondq_s are equal. Which is not, because the other signal, firstq_s is at "1111 1111 1111 1111". how can this be happening?!

 

[FvM]

the waveform shows that the output add_op_s and secondq_s are equal.

????
"0000 0000 0000 1010" + "1111 1111 1111 1111" = "0000 0000 0000 1001"
Looks reasonable in my opinion. According to the 16 bit target size, an overflow is involved, of course.

 

[jianhuachews]

omg so sorry... it is right i'm not in my right state of mind to do my work now because im sick. Anw yes, thanks! and with regards to what you mentioned
i had it changed to

process(add)
begin
       if (add='1') then
        add_op_s  <= firstq_s + secondq_s;    -- 17 bits <= 16 bits + 16 bits
        end if;
        
end process;
add_op<= add_op_s(15 downto 0);
overflow<= add_op_s(16);
end behavioral;

compiling works fine. but when i run simulation i had a fatal error when "add='1'" thus no output no nothing!!

 

[FvM]

but when i run simulation i had a fatal error when "add='1'" thus no output no nothing!!

Yes, that's understandable. You need to extend one of the input terms to 17 bits to make the addition work. E.g. like below:

add_op_s  <= '0'&firstq_s + secondq_s;

 

[jianhuachews]

oh yes it works!!! i didn't know i could program in such a way... thank you for guiding me so much FvM!!