# ** Error: C:\Modeltech_pe_edu_10.0a\examples\test_flipflop.vhd(23): Cannot read output "q".
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity flipflop is port(
ff_keyin: in std_logic_vector(15 downto 0);
ff_clk, ff_return, ff_rst: in std_logic;
q, qbar: out std_logic_vector(15 downto 0)); -- q is the first ff output, while qbar is the second ff output from q.
end flipflop;
architecture behavioral OF flipflop is
signal ff_return_int, done: std_logic;
begin
process(ff_clk)
begin
if(ff_rst='1') then
qbar <= (others => '0');
q <= (others => '0');
elsif(ff_clk'event and ff_clk='1') then
if(ff_return='1') then
q <= not ff_keyin;
ff_return_int <= '1';
elsif(ff_return_int='1') then
qbar <= not q;
end if;
end if;
end process;
end behavioral;
i want to obtain 2outputs ff outputs from the same input driven in. Everytime i press on "ff_return", the ff begins.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity flipflop is port(
ff_keyin: in std_logic_vector(15 downto 0);
ff_clk, ff_return, ff_rst: in std_logic;
firstq, secondq: out std_logic_vector(15 downto 0));
end flipflop;
architecture behavioral OF flipflop is
signal ff_return_int: std_logic;
signal firstq_s, secondq_s: std_logic_vector(15 downto 0);
begin
process(ff_clk)
begin
if(ff_rst='1') then
firstq_s <= (others => '0');
secondq_s <= (others => '0');
ff_return_int<='0';
elsif(ff_clk'event and ff_clk='1') then
if(ff_return='1') then
firstq_s <= ff_keyin;
ff_return_int <= '1';
else
ff_return_int <= '0';
end if;
if(ff_return_int='1') then
if(ff_return='1') then
secondq_s <= not ff_keyin;
ff_return_int <= '0';
end if;
end if;
end if;
end process;
firstq<=firstq_s;
secondq<=secondq_s;
end behavioral;
process(add)
begin
if (add='1') then
firstq_s(15 downto 12) + secondq_s(15 downto 12);
firstq_s(11 downto 8) + secondq_s(11 downto 8);
firstq_s(7 downto 4) + secondq_s(7 downto 4);
firstq_s(3 downto 0) + secondq_s(3 downto 0);
end if;
end process;
process(add)
begin
if (add='1') then
add_op_s (15 downto 0) <= firstq_s + secondq_s; --both firstq_s and secondq_s are 16 bits each, while add_op_s has 17 bits.
overflow_s <= add_op_s(16 downto 15); --most priority bit from add_op_s should go to overflow_s
end if;
end process;
add_op<= add_op_s(15 downto 0);
overflow<= overflow_s;
end behavioral;
process(add)
begin
if (add='1') then
add_op_s <= firstq_s + secondq_s; -- all signals here are 16 bits and it works here.
end if;
end process;
add_op<= add_op_s;
end behavioral;
add_op_s (15 downto 0) <= firstq_s + secondq_s;
????the waveform shows that the output add_op_s and secondq_s are equal.
process(add)
begin
if (add='1') then
add_op_s <= firstq_s + secondq_s; -- 17 bits <= 16 bits + 16 bits
end if;
end process;
add_op<= add_op_s(15 downto 0);
overflow<= add_op_s(16);
end behavioral;
Yes, that's understandable. You need to extend one of the input terms to 17 bits to make the addition work. E.g. like below:but when i run simulation i had a fatal error when "add='1'" thus no output no nothing!!
add_op_s <= '0'&firstq_s + secondq_s;
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