anjali
Full Member level 3
I'm new to FPGA. i have some queries.
unisims library in synplify_pro installation path consists xilinx components as black boxes.
unisims in xilinx installation path consists the definitions of all xilinx components (LUTs) & simprims library consists the definitions of multipliers,memories etc..
but SYNPLIFY_PRO tool can generate .vm or .edif files (netlists) with the complete definition of all the LUTs & our logic (our design).
how it can get the definitions of xilinx components? actually it have the components as black boxes in its instalation path.
where can we give the definitions path in SYNPLIFY_PRO?
unisims library in synplify_pro installation path consists xilinx components as black boxes.
unisims in xilinx installation path consists the definitions of all xilinx components (LUTs) & simprims library consists the definitions of multipliers,memories etc..
but SYNPLIFY_PRO tool can generate .vm or .edif files (netlists) with the complete definition of all the LUTs & our logic (our design).
how it can get the definitions of xilinx components? actually it have the components as black boxes in its instalation path.
where can we give the definitions path in SYNPLIFY_PRO?
