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Regarding UART modeling through FPGA.

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noloser

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I am modeling a UART interface using FPGA through VHDL, but there are some spec which i got confused. is the UART chipset found in most desktop PC decode a negative voltage as logic '1' or a positive voltage as logic '1'? I read some articles on RS232 communication, some saying one way while other saying the other, so i'm getting confused. can i safely assume that a start bit is logic '0' and end bit is logic '1' but not it's voltage level?

Thank for any useful information!!!
 

driver MAX 232 is inverting your signal after UART controller
 

does that mean when a design a UART interface on FPGA to communicate with the serial port on a desktop computer, i can just treat logic '1' as high voltage and logic '0' as negative (or zero) voltage level? any link to spec sheets or articles to show these info?

thank alot!!
 

After you have finshed your design in VHDL you'll need a driver RS-232 that is, it translate 3.3v or 5v or else logic level you have to a ±5V ÷ ±12V (the standard allow large voltage interval). Every converter, transmitter or receiver inverts the signal, then if you send a logic high (1) it is inverted by your transmitter (driver) and the receiver (driver in your computer) inverts the signal again.
Then for sure, a Start bit is allways '0' and Stop bit(s) always '1'.

This converters (drivers) are available from Linear Technology, Analog devices, Maxim, Texas Instruments .... and much more.

I hope this helps
 

MAX232 datasheet
**broken link removed**
 

which mean i will design the code such as logic '1' is high voltage and logic '0' is zero voltage and after completing, before using it, i need to design another driver circuit using the MAX232 chip, am i right?

Thank for your info!
 

Basically you can just invert the input as your shifting in/out (start bit is low).. then you use the max232 just for line drivers for the +12V/-12V.

jelydonut
 

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