prakashvenugopal
Advanced Member level 1
Dear Sir,
I am interfacing EDK in ISE. The GPIO of EDK is connected the ISE component through signal. while implement the design, it is shows the translate ERROR:NgdBuild:809 - output pad net 'Sig0_MC_compare' has an illegal load:
What could be the cause for this error? Please let me know.
I am using ISE 10.1.3
I am interfacing EDK in ISE. The GPIO of EDK is connected the ISE component through signal. while implement the design, it is shows the translate ERROR:NgdBuild:809 - output pad net 'Sig0_MC_compare' has an illegal load:
What could be the cause for this error? Please let me know.
I am using ISE 10.1.3