Regarding the non linear variation with respect to frequency change

[Maitry07]

Hello support team,

I am using a high-speed data converter with FPGA to measure the RF signal amplitude and phase. below is my query.
My RF input is a pure sine wave (no modulation). for a single normal operation, I am having the information of frequency based on which I am changing the NCO frequency to get the down-converted baseband signal and using 10*log(I^2+Q^2) to measure the amplitude from the captured I and Q.
now my front-end insertion loss is different for each different frequency. for example, my front end loss is 2 dB for 35 MHz RF input, for which I am adding 2 dB fixed digital gain compensation to get the correct amplitude output.
but when my RF frequency is 135 MHz, my front end loss is 3 dB. that means, my digital gain compensation value should be changed based on the RF input frequency information, right?
what would be the suitable way to do this for this kind of situation?

I am thinking to measure the approximate RF input frequency using the FFT algorithm and based on the measured RF frequency, I will prepare a look-up table for each frequency with respect to the required digital gain compensation value, which will further change the same.
Is there any best way to do above , kindly provide suggestions and feedback.


(FY: Once my RF input frequency changes, it will be constant for one single operation of 2-3 hours)

 

[stenzer]

Hi,

yes, the I and Q should not have a unit it's just a digital representation. You might say digits. So if the I and Q results in 1785 and 687, respectively, those are your digits. What I'm missing here is the conversion into the physical domain by means of the conversion into Volts. You are dividing your digital result by half of the "digital" input range. Here you have to map it to the physical domain by

V_I = 1785 • V_ref/2^N = xxx V​

V_Q = 687 • V_ref/2^N = xxx V​

​

where N are your number of Bits (here 15 as the 16th is the sign) and V_ref is the ADC's reference voltage (1.2 V or 1.8 V ?).

Can you provide aditional information of the ADC? I'm more interested in the DDC implementation as the datasheet states an ADC resolution of 14 Bit. As far as I know with a DDC you are not simply increase the resolution without addional signal processing, by means of oversampling and decimation. I'm not able to have a look on the full datasheet, as I have to request it.


BR

 

[Maitry07]

Hello,

Thanks for the quick response.
Actually, datasheet states ADC resolution of 14 bit which is typical.

DDC inside the chip I have configured as below.
NCO freq(MHz) = RF freq(MHz)- 3 MHz
DDC freq(MHz) = 3 MHz
DDC decimation rate I am using = 32 ( decimation rate)
ADC sampling rate right now I am using = 1966.08 MSPS
DDC output rate (MSPS) = 61.44 MSPS
DDC output data format = 16 bit digits ( signed ) FIX16_0 format

In the datasheet, Only full scale input power at device pin is mentioned , which is -2.2 dBm for my freq range (RF =30-70 MHz). but they have not mentioned in terms of V_ref. But I am assuming since it is RF-ADC , they have represent it in terms of dBm.

What I am assuming that -2.2 dBm = max full scale power (when there is no attenuation and as I am not using DSA- attenuator) = 0x7FFF ( in hex format) = 32767 ( in signed decimal format) If I consider 2^15 (for 1 sign bit and 15 number of bits =N)

--- Updated Jan 19, 2023 ---

Hello,

I have done reverse engineering to figure out what should the value of Vref?
I have taken below scenario.
RF input from my signal generator = -1.2 dBm
Verification of DDC output in terms of dBFS in my GUI = -1 dBFS.
as per datasheet, my full scale power is -2.2 dBm. (i.e, I should get -1 dBFS at -3.2 dBm)
But here I am having -1 dBFS DDC output at -1.2 dBm. , i.e. my board has 2 dB of RF front end insertion loss and when I set -1.2 dBm providing from my generator , -3.2 dBm should be received at the ADC pin.

Now, I have captured my I and Q digits in signed decimal .

I = 1206 ( signed decimal digit)
Q=-28882 (signed decimal digit)

Now, physical domain mapping as below.

V_I = [(1206 ) * Vref ]/32767 = 0.03680532242 * Vref V
V_Q = [(-28882)*Vref]/32767 = - 0.881435590 * Vref V

sqrt [(V_I) ^2 + (V_Q)^2 ] = 0.882203679 * (Vref)

I should get value of sqrt[(v_I)^2 +(V_Q)^2] Vpk = 0.218776 Vpk based on -3.2 dBm value

So, 0.218776 = 0.882203679 * Vref

Vref = 0.247988 V ( pk ) or we can say , Vref in pk-pk = 0.495976 V ( pk-pk), now If we convert this Vref pk-pk voltage into dBm = -2.11 dBm ( which is approx. as full scale given in datasheet)

So, Vref should be in the form of Vpk = 0.247988 V

That is my calculation.

I think , it is now correct.

Please check.

 

[stenzer]

Hi,

I'm still struggling due to the lag of informatin, by means of limited access to the full datasheet or even the user's guide to the development board. Are you using the teh development board (AFE7900EVM) at the moment?

Isn't there any hint how to convert the actual measured signal into dBm or Volts in one of the documents? Further, the limited datasheet states an ADC input reference impedance of 100 Ohm, and if we are talking about dBm, this makes quite some difference, have a look here [1].

[1] https://coretechgroup.com/dbm-calculator/

BR

 

[Maitry07]

Yes, I am right now using the development board. yes, it is written to have 100-ohm input reference impedance. but the development board is having the RF balun that converts this 100 ohm to single ended 50 ohm at the input end. so, at the board input, a single-ended 50 ohm impedance is there.

and no as the datasheet states it is RF-ADC, it only provides the characteristics in dBm. as the development board is having matching network along with the RF balun that converts the single-ended 50 ohm RF input to diff. ended for RF-ADC pins. the RF balun has typ. Insertion loss of 0.8 dB to 1 dB. my cable is having a 0.2-0.3 dB approx. loss. also, there is a matching network.

Now, as per their given GUI for the dBFS measurement at the output of DDC using captured I and Q samples, I am getting -1 dBFS at -1.2 dBm. so that is why I am assuming the approx. 1.8 dB to 2 dB loss of the front end.

Also, if we see for -2.11 dBm conversion in to Vpk ( voltage), it becomes 0.247988 Vpk. or 0.495976 Vpk-pk. ( for 50 ohm impedance) in the same calculator.

I have found one suitable article from analog regarding the conversion of dBFS to dBm for this kind of ADC. which has the reference of Vref equivalent to full scale power. https://ez.analog.com/wide-band-rf-transceivers/design-support/f/q-a/542283/dbfs-to-dbm-calculation

So, full scale power in dBm(-2.11 dBm) is equivalent 0.247988 Vpk

 

[stenzer]

Hi,

by doing the math I'm ending up with a quite similar FS-input-voltage-range.

-2.2 dBm = 10 • log( (V_RMS^2/50 Ohm) / 1 mW)​

10^(-2.2 dBm / 10) = V_RMS^2 / (50 Ohm •1 mW)​

V_RMS = sqrt( 10^(-2.2 dBm / 10) • 50 Ohm • 1 mW) = 173.5741 mV_RMS​

Vpk = V_RMS • sqrt(2) = 245.4709 mV_pk​

Vppk = 2 • Vpk = 490.9418 mV_ppk​

In doubt, I would double check in the ADI as in my experience their engineers are quite responsive.

BR

 

[Maitry07]

Hello,

yes, thank you for the detailed support. I will be waiting for your double check verification response.

 

[Maitry07]

Hello,
As per above , I have verified output in dBFS and through DSP to generate SQRT(I^2+Q^2) and both are giving same results. based on which I have figure out that my RF front end Insertion loss is 1.5 dB.
Now I need to add this fix compensation (addition) to the result. So, how to add this fix compensation? which was my original question.

 

[stenzer]

Hi,

your aim is to determine the amplitude of an excitation/transmit signal, where your only prior is its frequency. Now as you have verified that your receiver attenuates the measured TX signal by 1.5 dB, you have to compensate this attenuation by adding it to your determined amplitude/power, measured by your receiver. E.g. your measurement leads do (arbitrary chosen) -31 dBV, your actual TX signal is -29.5 dBV.

So if your receiver shows a flat behaviour over your frequencies you simply add this 1.5 dB. If not flat, you need a look up table and characterize the receiver for various frequencies within your target frequency span.

BR

 

[Maitry07]

Hello,

Yes I got your point.

But as my final output is in the form of Vpk ( SQRT(I^2+Q^2)). so , when we think of providing fix 2 dB addition in terms of Vpk , it is not linear.

Example
If I want to add 2 dB for the measured amplitude of 0.0031622 Vpk ( -40 dBm) , I need to add 0.000818871 Vpk to get 0.0039810717 Vpk( -38 dBm).

But If I want to add 2 dB for the measured amplitude of 0.02511886 Vpk(-22 dBm), I need to add 0.006503916 Vpk to get 0.031622776 Vpk(-20 dBm)

So, It is not a correct way to add the fix dB compensation at my Vpk output. so, my question is , assuming my receiver has the flat response of 2 dB insertion loss all over the frequency band and I am getting the result in Vpk , then how to add this fix 2 dB?

 

[FvM]

Did you realize that adding a fixed dB correction corresponds to multiplicative magnitude correction factor?

 

[stenzer]

Hi,

as FvM pointed out, if dealing with dB (log) you can easily substract and add values, where this substraction and addition corresponse to a division and multiplication, respectively. See https://www.rapidtables.com/math/algebra/Logarithm.html

BR

 

[Maitry07]

Hello,

Yes, I understand your point. thank you for your detailed guidance and support.