Regarding the clarification of FPGA Hardware Design ( XC3S50AN)

[prakashvenugopal]

Hi,

I had designed the FPGA board with ( XC3S50AN) (TQ144 Package) as attached image. In that FPGA IC, the red mark Portion is heat sink.? we should not have plated through hole in that area? I had placed the decoupling capacitor with Plated through hole in that area. Please let me know.

Thanks,
V. Prakash

https://obrazki.elektroda.pl/58_1325825377.jpg

 

[Marcel Majoor]

Have a look at UG112, the Device Package User Guide from Xilinx.

In short, if you are not using the heatsink type (or don't glue it to the board), then there is no worry I guess.

From page 26:
"In the die-up/heatsink-down configuration, the heatsink surface is insulated"

Page 56:
"Some of the heatsink packages – like HQ, with the exposed heatsink on the board side – can be glued to the board with thermal compound to enhance heat removal into the board. BGA packages with full matrix of balls can be cooled with this scheme. Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources, particularly if the board is not cooled effectively. An otherwise cooler component can be heated by other heat-contributing components on the board."