Regarding the 10 MHz reference clock generation from Zynq FPGA

[Maitry07]

Hello support team,

I have a requirement for 10 MHz clock generation (single ended -sine wave ) for my outdoor unit LNB through FPGA (zynq-7000 series). so is it possible to use below.

40 MHz TCXO interface to Clock capable pin >> Use of clocking wizard for the generation of 10 MHz >> assign the clocking wizard output to one of clock capable pin>> apply signal conditioning>>> single ended 50 ohm 10 MHz reference output.

--- Updated Mar 28, 2023 ---

Is the above suitable option for 10 MHz clock generation ?

 

[FvM]

FPGA PLL adds considerable jitter to the clock, you should check the datasheet specification against your requirement.