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Regarding synthesizable DELAY concept...

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rakesh_aadhimoolam

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hello.......

can we be able to make a synthesisable delay model.....

i mean""""given a 1MHz signal it has to be outputted after a 1 ms delay and there shoold be vhdl code for it which is synthesizable""""""
 

spauls

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No,
Synthesis tool will ignore all kinds of DELAYS
 

steven852

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yes, synthesis tools will ignore all delay lines except you use "dont_touch" command.
 

bansalr

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The abstract way of delaying may be used with delayingw.r.t clock timing.
i.e. introduce FLIP FLOP or use a RAM to delay if it is a mulitple of clock pulse width.
 

vipulsinha

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Yes you can do that but the synthesis tool Just ignores the AFTER clause if you are using. The best way to do is to make a counter and output the design output after specific counter count that satisfies your delay

vipul
 

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