Regarding SYNOPSYS Design vision cmd - rtl2saif

[sabhp143]

Hi guys,

I am new to edaboard. I want to estimate the power consumption of a circuit. I found many tutorials on how to do synthesis and then generate saif file and use them to estimate power. when i tried following the same i am able to synthesize the file but when i type the command rtl2saif to generate the saif file it says the command is unknown. I have tried it in synopsys design vision and also in synopsys dc_shell. Appreciate any help.

 

[jbeniston]

Do you not mean vcd2saif?

If so, it should been run from the Linux shell, not from within dc_shell.

 

[sabhp143]

Do you not mean vcd2saif?

If so, it should been run from the Linux shell, not from within dc_shell.

HI Thanks for the reply. Its not vcd2saif it is rtl2saif. What i am trying to do is power estimation using synopsys. I want to find the switching activity for a given circuit and find the power consumption.


"In Design Compiler, in order to run the rtl2saif command, you first need to set the variable power_preserve_rtl_hier_names to true and then analyze and elaborate your design normally (you may also save the elaborated design if you want):

set power_preserve_rtl_hier_names true
analyze -format vhdl -library WORK ./SRC/adder.vhd
elaborate ADDER -architecture rtl -library WORK -parameter "N=16"
rtl2saif -output ./SYN/SAIF/adder_rtl_forward.saif -design adder_N16
write -hierarchy -format ddc -output ./SYN/DDC/adder_N16_elaborated.ddc
quit

"


The cmds above are one i tried. Its from a tutorial -- **broken link removed**


when I type cmd rtl2saif in design vision it says cmd not found.



If possible can u suggest some other tutorial. Thank you and have a great day.

 

[jbeniston]

I think that tutorial is out of date. Have a look in the help at saif_map.

For a tutorial, look at the Power Compiler user guide.