Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

regarding si analysis

Status
Not open for further replies.

p.sivakumar

Member level 1
Joined
Dec 29, 2005
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,617
Hello friends

Any one can clarify my doubt ?

i didn't understand the exact difference between glitch and noise
because for doing si analysis by using cadence celtic,we can do glitch analysis and noise analysis seperate seperately by using different flows and we can do both analysis at a time .

for that first i need to understan what is glitch and what is noise ?

I know that those are generated due to the formation of coupling capacitance between two nets running paralelly

can you provide any useful si related materials ?

Thanks & Regards
siva
 

Hi Sivakumar,


Glitch is a small blip which occurs when the difference in data arrival times at the input pins is more than the delay propogation of the gate.

As u told noise is a result of capacitive coupling between nets.

Hope this helps.

Rgds,
Rakesh
 

Hi ,

Please look at SOLD from synopsys ( in Primie time user guide ) .....

Thay have excellant explanation for the same .

Thanks & Regards
yln
 

when aggeresor is swithing and victim is in stable state then glitch will be geneted on victim net.
and noise will be generated beacause of the cross coupled capacitance of the nets the effect of nosie is glich.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top