Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

regarding place and route

Status
Not open for further replies.

kishore111281

Newbie level 6
Joined
Feb 19, 2008
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,362
Hi after doing place and route will it reduce my dut's frequency, if so why? please correct me if i am wrong.
 

hqqh

Full Member level 4
Joined
Feb 7, 2002
Messages
195
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Activity points
1,602
Hi,
the placement and also the routing have an impact on the parasitic resistances and capacitances. Therefore you normally you will carry out an parasitic extraction after place and route and do a post-layout simulation. Then you will get your "final" design operating frequency.
Regards,
hqqh
 

kishore111281

Newbie level 6
Joined
Feb 19, 2008
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,362
thank you, i didnt get exact answer , my doubt is effect of place and route on frequency , whether it will increase or decrease.
thanks in advance.
 

Saravanan.G

Junior Member level 1
Joined
Oct 12, 2007
Messages
19
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
Bangalore,India
Activity points
1,395
Place and route blocks are not optimized like custom layout.
some optimization is done using timing driven placement.
RC of routings plays role in P&R blocks.
P&R tool does not optimize inside cell level and uses existing std cells.
In custom layout both cell layout and routings signal can be optimized.
 

asicganesh

Member level 3
Joined
Oct 18, 2007
Messages
58
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,288
Activity points
1,681
Kishore you just generate the netlist (schematic or circuit connections) after synthesis, which takes the maximum delay path and calculates the Frequency for your design..

Say now this schematic has to be fabricated on a die of much smaller size.. lot of parameters come into picture.. like routing delay, paracitic capacitance, si, etc.. which affect the circuit operation, frequency, etc.

Hence after P&R by Backend team.. the Frequency may decrease/increase..
 

kishore111281

Newbie level 6
Joined
Feb 19, 2008
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,362
thank you , I got the answer with respect to ASIC, suppose if i am going for FPGA , will it be the same as that of ASIC. Why i am asking is i have designed some modules for perticular design , but when i am done with synthesis it has given one frequency , but after doing P&R some modules got raise in frequency and some module lost frequency.
Thanks in advance.
 

mahmoudgazzar

Newbie level 4
Joined
Oct 5, 2007
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,306
i think a raise in frequency is a bit awkward ....i may mean that the previous calculation was fault or the current one is the faulty one .....
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top