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the placement and also the routing have an impact on the parasitic resistances and capacitances. Therefore you normally you will carry out an parasitic extraction after place and route and do a post-layout simulation. Then you will get your "final" design operating frequency.
Place and route blocks are not optimized like custom layout.
some optimization is done using timing driven placement.
RC of routings plays role in P&R blocks.
P&R tool does not optimize inside cell level and uses existing std cells.
In custom layout both cell layout and routings signal can be optimized.
Kishore you just generate the netlist (schematic or circuit connections) after synthesis, which takes the maximum delay path and calculates the Frequency for your design..
Say now this schematic has to be fabricated on a die of much smaller size.. lot of parameters come into picture.. like routing delay, paracitic capacitance, si, etc.. which affect the circuit operation, frequency, etc.
Hence after P&R by Backend team.. the Frequency may decrease/increase..
thank you , I got the answer with respect to ASIC, suppose if i am going for FPGA , will it be the same as that of ASIC. Why i am asking is i have designed some modules for perticular design , but when i am done with synthesis it has given one frequency , but after doing P&R some modules got raise in frequency and some module lost frequency.
Thanks in advance.