Regarding LVS match in Cadence in UMC180

[sumeetanwikar]

Hello,

I have designed an inverter and its layout. I have provided pins in schematic but not in layout. But still LVS match is clean. It should not match as pins are not present in layout. I am using UMC180 with assura. So help me setting up files in Cadence for LVS check?

Thanks and Regards,
Sumeet

 

[erikl]

If the layout-to-schematic mapping is unambiguous, the LVS can still match without the layout pin names. However I'd advice to add the pin names in layout nevertheless - for later recognition - unless you just want to hide this. Nothing else has to be done with the setup files.

 

[dick_freebird]

Depending on the PDK and the LVS run-settings you could
see terminal mismatch flags - not in this case, evidently.
But I've worked in kits where terminal match is enforced.