Regarding how to make tristate based designs synthesizable

[pavankumarmnnit]

lattice internal tristate

Hi everbody,
I am having design(vhdl) for banyan switch in which there is condition that some ports should be blocked in certain situation.. so,"It is compulsory that i should use tristates in my design".


I did coding and synthesized using xilinx ise simulator there it gave warning regarding tristates but it is synthesized and i verified simulation also .For further generation patterns using i need to do "dft compiler synthesis" .

I am unable to do synthesis in design compiler because of tristates in my design . the error is unable to resolve tristate conflicts. I have inout or buffered ports which are blocked in some situation in my code................

Try to help in this matter...............

Thanks in advance...................

 

[FvM]

I guess, you are talking about internal tristate nodes?

 

[FvM]

Re: Regarding how to make tristate based designs synthesizab

I have been using internal tristate in some FPGA designs with &#65ltera Qu&#97rtus and also with Precision RTL synthesis in the Lattice toolchain. I assume, that they are available with other HDL synthesis, too.

To understand the restrictions in synthesis of internal tristate nodes, it's important to know, that CPLD, FPGA or ASIC have no real internal tristate capability, only unidirectional point-to-point connections between logic cells.

Thus an internal tristate construct has always to be translated to multiplexers. In a real tristate circuit, multiple drivers can drive out simultaneously (although causing a bus contention). This can't happen in multiplexer circuit, all concurrent enable signals for a particular tristate node must be combined to an unequivocal multiplexer select signal.

Internal tristate conflicts respectively synthesis failure ususally happens, if no clear multiplexer select condition can be found. This may be the case, cause the select conditions are actually conflicting or at least unknown in part. You have to change the design to remove the problem. As a simple rule, all select conditions should be derived by asynchronous logic from the same signal set in an exclusive way.

The other option would be to use multiplexers instead of tristate nodes explicitely in your design.

 

[pavankumarmnnit]

Re: Regarding how to make tristate based designs synthesizab

if(s1='Z' and s2='0') like this so many conditional statements using Z were there in my program .......


I controlled Z by using enable when it is output node but internally should i use signals to control ........


what about if statements based on Z . I need some signals to be set when s1='Z' etc.................

 

[FvM]

Re: Regarding how to make tristate based designs synthesizab

I need some signals to be set when s1='Z'

But it isn't possible. An input signal can be either 'H', 'L' or unknown (in simulation only). Of course with internal tristates you can use an OR function of all tristate enables instead.