regarding cycle based symulators and event based symulators

[mallikmarasu]

hi every one ,

can anyone explain cycle based and event based symulators clearly..



regards
mallikarjun

 

[pradeep2323]

Re: regarding cycle based symulators and event based symulat

hi malligaru,
cycle based simulators are usefule for synchronous designs where operations happen only at active clock edges works on cycle by cycle basis.timing information between two clock edges is lost.
significant performance.

event based simulators processes elements in the design only when signals at the input of these elements change.intelligent schedulling is required to process the elements.

 

[barkha]

Re: regarding cycle based symulators and event based symulat

Event-Driven Simulators
An event-driven simulator, as the name implies, evaluates a component, whether it is a gate or a block of code, only when there is an event at an input or sensitivity list of the component. An event is a change of value in a variable or a signal. If an event at a gate input causes one of its outputs to change, all the fan outs of the gate will have to be evaluated. This event ripples throughout the circuit until it causes no more events, at which time evaluation stops.


Cycle-Based Simulators
The other extreme in the simulator spectrum is cycle-based simulators. To motivate the need for cycle-based simulators, consider the combinational logic that computes the next-state function for a finite-state machine. Every time the FFs change, many events are generated in the combinational logic, but only the steady state is latched at the next clock edge; evaluations of all intermediate events are wasted. To avoid evaluating transient events, cycle-based simulators take in the steady-state values of the FFs at the current cycle, regardless of whether a state bit has changed, and apply the next-state function combinational logic to compute the inputs to the FFs for the next cycle. In other words, the combinational logic is evaluated at each clock boundary and a gate is evaluated once, regardless of whether its inputs see events. Therefore, for a circuit to be simulated by a cycle-based simulator, the circuit must have clearly defined clocks and their associated boundaries. Consequently, asynchronous circuits and circuits with combinational loops cannot be simulated by cycle-based simulators. Furthermore, because only steady states are computed, all delays in the circuit are ignored in cycle-based simulation. All components are assumed to have zero delays.
•Cycle-based simulators work off of a control and data-flow representation
•Treats everything in the design description as either clocked element or zero-delay combinational logic
•Advantages
– exceptionally fast
– same internal representation for both simulation and synthesis
– predicted results same as synthesized logic

 

[shiv_emf]

event based simulator .. !!
what if clock transition is considered as event..thn will thr be any difference !.....
at every clock transition ... values r updated..hence do v require any distinction between two types of simulators?
Shiv