Regarding Clock Latency and Skew?

[RGR]

Hai everyone

In my project , at cts stage , after clock routing

Trail 1:
clock skew : 100ps
clock latency :600ps


Trail 2:
clock skew : 200ps
clock latency : 400ps


Which trail is better and why?

please help me.I am using ICC and encounter tool


Thank you

RGR

 

[neetendra1]

Hi RGR,

The trial 1 and trial 2
it depends upon following
1. what is your block size.
2. Power requirement of the block.
3. CTS structure to TOP clock structure.
...

 

[sharath666]

Maybe you need to check for timing performance. Only then you will be able to decide.

 

[rca]

you should also check:
1- number of the number of buffer added by the post cts setup fix
2- number of the number of buffer added by the post cts hold fix

 

[rahul.achates]

I think skew should be having more priority .. which is very much important to meet. check your design specification for skew and latency limit.

 

[ivlsi]

you should also check:
1- number of the number of buffer added by the post cts setup fix
2- number of the number of buffer added by the post cts hold fix

Could you elaborate please (explain in details)?