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regarding Clock generation

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Member level 4
Aug 19, 2007
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Hai friends,

Thanks for giving best replies,

Let me get cleared in one more confusion

Writing HDL will generate clock fine, this in front end.

Clock gets generated.

Coming to backend how this generated clock comes into picture?

After synthesis we get a netlist . do this netlist includes the hardware of clock?

Then we design a IC where clock has to be given as input, normally oscillator are used.(We say for a microprocessor connect 32.5Mhz clock to the clock input PINs)

Now what is use of the clock we generated using HDL and what is the use of Oscillator clock.

I am unbale to understand the difference



The name generated clock itslf means " it is derived from source clock".
The generated clock in the sence, the microprocessor will take the OSC clock as a input.
From your point of view the clock freq is 33... Mhz, but My processor required any frequency less than this. In this case internally in the chip the clock may be devided by using sequential logic or any PLL's.

I hope this clears your doubt.


actually the clock oscillator is the source of the clock ie it generates the clolck pulses. and when coming to hdl coding this clock that is actually generated by the oscillator is used.
ie clearly we can say that the hdl coding does not generate clock but it uses the clock that is generated by the oscillator. with reference to the clock we will do the operation that is required to process.

hope it helps
with regards

Dear designer,

my 2 cents in this discussion...

RTL is a way of an abstraction, where when you refer to a clock definition in the sequential block ,means what clock your flop works and what logic you want to capture and all that stuff.

When you see Chip as a whole
1. The clock is given at the Clock pad, usually a slow frequency clock, due to the limitation of the Pad's and noise issues.
2. The clock is inputted to the Clock Generation Unit block(usually all most all the Chips have this), this block will have PLL(Phase locked loop), the purpose of this block is to Generate all the clock frequencies.
3. In the stage of Place and Route we build Clock -tree's for these specific clocks and ensure those specific clocks arrive at the same time to all the relevant flops .
4. It is the logic which determines whether the data is valid across clock-clocking interfaces and all that stuff...

hope i did not complicate the problem of your understanding.

Praise the Lord

best regards,
[Learn ASIC design for free]

Clocks are generated physically by crystal oscillators and given to the circuits as a signal..

iam working on board design so i could able to answer the question as

in our board design we use common clock that is crystal for the board and from that using the clock buffer we send the clock to all parts of the board and also we will use fpga in our board so we give clock to fpgapin also so that we can use the clock.
using this clock we will operate the logic inside the FPGA.
hdl code using this clock will be operated.
usually this clock is given to all components that requires the clock and also to FPGA.

in our case we doesnot generate any clock inside fpga for hdl coding. we actually utilize the clock that exists on the board.


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