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Regardin async FIFO verification of cummings paper in SysVer

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vlsi_maniac

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i am new to verification and i was given this task of verifying async fifo.
i was given FIFO design based on the paper "simulation and synthesis techniques for asynchronous FIFO design" by cummings
i have written a nominal testbench in verilog which just checks FIFO functionality.
i have done a decent work on system verilog design but this is the first time i have to verify something.
how should i proceed in system verilog and what are the considerations to be taken
thanks for all
 

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