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Reg synthesis(optimization constarints)

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engr

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dc set max_area 0

Hi All,

Among the optimization constraints, i seen the are "max_area" constraint always setting to 0, what it really mean, i could not able to visualize whats difference between
set max_are 0 and set max_are "other than zero".

These constraints we are setting while we synthesize the RTL, max_area constraint is applicable to each and every gate inferred by tool or to the whole RTL module we synthesizing.

If some docs gives good picture on this ,pls provide that.

Thanks in advacne

Added after 1 minutes:

How should i exactly find(estimate) max_area constraint in DC(desing compiler)
 

Among the optimization constraints, i seen the are "max_area" constraint always setting to 0, what it really mean

During synthesis, we used the max_area 0 constraint to minimize the area of each module without violating the timing constraints.
Usually, we try to get the smallest/optimize area as possible.

Frankly, I've never seen a DC script uses max_area set to other than zero.
Perhaps, someone can share his/her thought on this issue if he/she have used max_area set to other than zero.

Hope it helps.
 

    engr

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