Reg" set_clock_latency

[energeticdin]

set_clock_latency

Hi All,

Please let me know, what is the value we have to given in general,

set_clock_latency:

I came to know that 30% of clock period for input delay and output delay
For setup uncertainty 10% of clock period?

Plz let me know this is rite? and how much we have to give for clk_latency?

Dinesh

 

[dcreddy1980]

Hi Dinesh,

There are two different things for Set_clock_latency, one is Source latency and the other is Network latency.

Incase of Network latency, it depends up on the number of flops present inside the block and this number can availabe from place and route guy based on number of flipflops inside your design or you can just put a certain number and give to the place and route and based up on your floor plan and size of the block, after place and route, we can get more clear latency number. This can be applied for later synthesis runs.

For Source latency, you have to know where your clock generation circuitry is present and based on the placement of this circuit, your source latency will vary. This information you can get from floor planning about the location of this module and how far it is from your block to be synthesized.

Regards,
dcreddy