energeticdin
Full Member level 2
Hi,
I read that negative setup time requirement, the data may arrive at the pins of the device after the relevant clock edge arrives at the pins and the data will still be sampled correctly. This means that internal to the device, the clock experiences a larger delay relative to the data, so that when they both arrive at the internal circuitry that samples the data, the data arrives before the clock signal does.
So for setup, in D pin
if delay of 1ns is added in clock
path then resulting circuit will have setup time of (–0.5 ns).
SO setup violation is reduced much.
Am i ritte?
Then why cant all flops made in ff with negative setup ?
Please give me some more info about Zero setup time?
Thanks
DIN
I read that negative setup time requirement, the data may arrive at the pins of the device after the relevant clock edge arrives at the pins and the data will still be sampled correctly. This means that internal to the device, the clock experiences a larger delay relative to the data, so that when they both arrive at the internal circuitry that samples the data, the data arrives before the clock signal does.
So for setup, in D pin
if delay of 1ns is added in clock
path then resulting circuit will have setup time of (–0.5 ns).
SO setup violation is reduced much.
Am i ritte?
Then why cant all flops made in ff with negative setup ?
Please give me some more info about Zero setup time?
Thanks
DIN
