Do you have any digital delay locked loop circuit papers or materials regarding digital DLL which can be implmented using the Verilog or Vhdl simulation tools completely .
Also can you tell any method by which i can use a Digital simulation tool (FPGA ADVANTAGE PRO) circuit output to GIVE to an analog simulation tool (Tanner/Tspice) signal circuit input ..
Do you have any digital delay locked loop circuit papers or materials regarding digital DLL which can be implmented using the Verilog or Vhdl simulation tools completely .
Also can you tell any method by which i can use a Digital simulation tool (FPGA ADVANTAGE PRO) circuit output to GIVE to an analog simulation tool (Tanner/Tspice) signal circuit input ..
u can just use it for simulation coz it gives only the behavioral model of the building blocks of dll, from which u can know what constructs a DLL and how it works.
There is some errors in the verilog code from stanford. Also some codes are missing in the submodules. Can you verify the working of code and post the good working code .