hihktk said:hi, DenisMark
I have tried the method you mentioned above, but the simulation result is the same as the figure posted. The load capacitor of the BGR output VREF is very small, so I think it can be neglected.
hktk said:here is our simulation result, the red line is the node VREF1 and the yellow one is the node VSSA with bonding. does the roll of the red line due to low loop gain or phase margin ?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?