Reference Osc. selection for dual freq synthesizer

[robismyname]

Im trying to design a superhet radio with a dual frequency synthesizer, part number ADF4252 https://www.analog.com/static/imported-files/data_sheets/ADF4252.pdf.

Not sure if this is relevant but my 1st IF is 170MHz, 2nd IF is 10.7MHz. VCO range for 1st IF is 1550-2500. VCO range for 2nd IF is 75-150. Spacing between channels will be 1 MHz.

Obviously the synthesizer requires an oscillator, but I am not certain will any standard frequency (i.e. 11.059MHz, 12.XXX, 14.7456MHz, etc.) will do. Please offer advice.

 

[BigBoss]

Its PLL is fractional, so channel spacing must NOT be as the reference frequency.Look at page 11.
But 12MHz is quite cheap and easily available one..

 

[robismyname]

Its PLL is fractional, so channel spacing must NOT be as the reference frequency.Look at page 11.

What details on page 11 gives you this insight? Are you referencing a figure or a formula?

But 12MHz is quite cheap and easily available one..

Where on page 11 tells you that 12 Mhz oscillator is ok?

As you can see my knowledge of PLL's is tenuous. PLease provide a little more detail.

 

[kspalla]

Hi,
How can the frequency plan is so bad.
1st IF is 170MHz and 2nd if is 10.7 then the 2nd lo will be 170-10.7 i.e. 159.3MHz and is fixed. This will be impossible if the bandwidth is 1MHz.

The selected part works in this range and simple 10MHz should be OK.

 

[robismyname]

Hi,
How can the frequency plan is so bad.

How come the frequency plan is so bad? That is because I quoted the wrong 1st IF frequency. I should have wrote 140MHz not 170MHz, sorry. so now the 2nd Lo is 129.3MHz not 159.3 MHz

1st IF is 170MHz and 2nd if is 10.7 then the 2nd lo will be 170-10.7 i.e. 159.3MHz and is fixed. This will be impossible if the bandwidth is 1MHz.

The selected part works in this range and simple 10MHz should be OK.

Again I need specifics on why it will be ok, what is your reasoning for saying this?

 

[RFDave]

Dean Banerjee has an excellent App Note/Book at National Semiconductor on PLL design.

**broken link removed**

An integer-N PLL has to have an integer as the ratio of the VCO frequency and the comparison frequency. For example, a 200 kHz comparison frequency will give you output frequencies that are multiples of 200 kHz. Generally, there is a divider between the reference oscillator and the PFD, so you can use a 12 MHz Reference Oscillator, divide it by 60, and get a 200 kHz comparison frequency.

I'm not sure why kspalla thinks your frequency plan won't work. Your 2nd IF needs a 100 kHz comparson frequency, but that shouldn't be a problem.

The equation on page 11 that BigBoss is looking at is equation 1 and 2. Read the text around that one. This indicates that there doesn't need to be an integer relationship between the comparison frequency and the VCO Frequency. For example, you could use Fvco/Fcomp = 12.3402 and have the dividers give you that ratio.

Take some time and look through Dean Banerjee's book, that should answer most of your questions. Analog devices also has some software you can download and use for design, I think it's called easypll.

Dave
www.keystoneradio.com




Since the ADF4252 is a fractional N synth

 

[kspalla]

I said "impossible" as the information was wrong(170 --->140MHz).

If you already selected the part number, easy way is just contact the vendor for assistance. You can use his tool to set the registers and can find the step size.

As it is dual down conversion you can use the 2nd LO for finer selection. This is because 1st Lo may not be tunable over the wide range with the step you may need.

Hope this solves.

Added after 32 minutes:

You can use this tool "http://designtools.analog.com/dt/rfpll/adf4X5X.html" to check the feasibility.