Thank you so much! That chip is a much better option for what I need.
Another question if you dont mind, its more of a general question about PLLs. For my lab testing I am created a kind of PLL.
I am using a HP frequency synthesizer to create my 1.5 GHz reference, a balanced mixer as my phase detector, and a 10KHz low pass filter as the loop filter. The microcontroller samples the PLL output and adjusts the VCO accordingly.
Since I am using a balanced mixer as my phase detector, the filtered down converted spectrum contains the difference frequency between the ref and VCO output, usually a signal in the mHz to 10Hz range. That makes sense to me, and its how i maintain stability, by keeping that frequency as close to zero as possible.
How do these chip sets perform their internal PLL? Do they too use a microcontroller or digital circuitry like the example above? Or is there a much more elegant analog solution to maintaining loop stability?
Bonus question:
If I am using a mixer topology like above, will I ever see a DC offset on the output? If my loop filter has a low enough cut off to attenuate (ref - VCO) I can't get my loop to work. But if i set the filter high enough to keep that mHz - 10 Hz signal, i can get my loop to stabilize. I will freely admit, user error here is very likely.
Thanks in advance,
Sami