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Reference Buffer: For high Speed pipeline ADC

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sachinagg77

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dac reference buffer

For my pipeline ADC [110MHz] design, I need to design an internal reference buffer circuit, to provide reference to my MDAC circuit. I would be grateful if some one could provide some referenced for voltage buffer design [for high speed Switched Capacitor Circuit].

Thank You
Sachin
 

philipwang

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voltage reference buffer

Dear Sachin,

MDAC is decoder which transfers 11 10(or 01) and 00 to -Vref, +Vref and 0, so just one Vref reference voltage is needed, right?

Where 11 10(or 01) and 00 is the output of comparator.

What is your exact mean? Vref genarator design of other problem?

Regards,

sachinagg77 said:
For my pipeline ADC [110MHz] design, I need to design an internal reference buffer circuit, to provide reference to my MDAC circuit. I would be grateful if some one could provide some referenced for voltage buffer design [for high speed Switched Capacitor Circuit].

Thank You
Sachin
 

sachinagg77

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reference voltage buffer

Dear Philip Wang

Thanks for the response. You are correct to say that only three references -VREF, +VREF and 0 are required for the MDAC circuit. These levels have a DC level that is different from zero [say VCM]. So, I need three references now, that is, VCM+VREF, VCM and VCM-VREF.

I need to put a "buffer" each between the references VCM+VREF and VCM-VREF and the DAC reference inputs to prevent the noise from MDAC from influencing other circuits that share these references.

I am facing problem in the design of this buffer and would appreciate if you could help me with some references.
 

philipwang

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adc reference buffer design

Dear Sachinagg77,

I see. You need one buffer between reference generator and the MDAC ref-voltage input, to prevent the MDAC noise influencing the reference generator.
Right?

I think just one simple unit-gain amplifier is needed.
More simple, you can increase the shielding cap. between the reference generator output and gnd to filter the noise.
Actually, I don't think the noise has much influence, adding shielding cap. is more advisable.

Just for your reference. Good luck!
Regards,


sachinagg77 said:
Dear Philip Wang

Thanks for the response. You are correct to say that only three references -VREF, +VREF and 0 are required for the MDAC circuit. These levels have a DC level that is different from zero [say VCM]. So, I need three references now, that is, VCM+VREF, VCM and VCM-VREF.

I need to put a "buffer" each between the references VCM+VREF and VCM-VREF and the DAC reference inputs to prevent the noise from MDAC from influencing other circuits that share these references.

I am facing problem in the design of this buffer and would appreciate if you could help me with some references.
 

lgqfang

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reference buffer

i think the buffer related with the stucture adopted to pruduce the diferencial voltage reference.
 

sachinagg77

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Dear Philip Wang

I am sorry for the delayed reponse.

As you suggested, using a capacitor between the reference output and the ground is the simplest way out. But owing to the high frequency involved [ADC clock =110MHz], a high value of capacitor is required. Using an external capacitor of 1uF or more results in unwanted effects due to parasitics related to package pin etc.

To avoid this, I would like to use a internal buffer. I would appreciate if you could send across some reference that details the design of such buffer [I think using an op-amp in voltage follower configuration would require an op-amp of very high specs]. Do you know of any other approach?

Thanks for your feedback.

With Regards
Sachin Aggarwal
 

hubert008

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It's a real problem for pipeline ADC, because the reference stand for the linearligy of MDAC. It is a system and difficult to design. The simple method is to use resistor and the volitage from bandgap. Use the equation to decide the ration of resistors.
 

philipwang

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Resistor divide voltage is not an advised approach, because the resistor can't filter the noise, but it is the noise that affect the stability of th reference voltage.

Maybe one voltage following OPA buffer is needed. No any oyher approach is advised by now, sorry.

Best regards,
 

sachinagg77

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Philip Wang is absolutely correct. The resistor divider is not a good approach for this 110MHz sampling rate ADC. A buffer is essential. Proper implementation of this buffer is a proving to be difficult. Any suggestion for this buffer design will be helpful.

Thank You
Sachin
 

megzhuy

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Try to find some patterns or papers.
 

spbhu

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Class AB opamp is required!
 

Btrend

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there are 2 solutions:
1.
use a high BW (low output resistance) buffer with "enough" decoupling cap. But this solution involving closed loop, u should calcuate how large is ur noise from MDAC, and how fast of "recovery" time u needed.
2.
Use a current mirror with "enough " biasing current & "enough" decoupling cap.

p.s.
the decoupling cap is for transient current surge from ur MDAC.
 

sachinagg77

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Btrend said:
there are 2 solutions:
1.
use a high BW (low output resistance) buffer with "enough" decoupling cap. But this solution involving closed loop, u should calcuate how large is ur noise from MDAC, and how fast of "recovery" time u needed.
2.
Use a current mirror with "enough " biasing current & "enough" decoupling cap.

p.s.
the decoupling cap is for transient current surge from ur MDAC.

Thank You Btrend.

I apologise for the delayed response. I understand the first point you mentioned but could not understand the second one. What do you mean by using "Current Mirror" as buffer? Could you please elaborate a bit?

Regards
Sachin
 

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