reducing parasitics in mim cap

[hacksgen]

mimcap top plate bottom plate

hi everyone,

I would like to know if there is any means to suppress the parasitic capacitances in mim caps. The technology used in a umc 0.18um imager technology which has 4 metal layers and the mim cap is between m3 and m4 layers. I am designing a charge redistribution sar adc for 12 bit resolution and i think the parasitic might play a significant role in this design. Any suggestions on how to reduce the parasitic capcitance for a given unit capacitor C.

Thanks

 

[sat]

fringe cap in nwell

Do you mean - during extraction you want to avoid double counting of parasitic caps? - if yes - you have to use blocking techniques during RC extraction.

If you mean reduce parasitic C from plates to nearby routed metal interconnects - and reducing decoupled cap to substrate [gnd].. then read the following :

I don't know - technique to suppress it completely/or substantially - don't think of shielding - that is going to increase it further.

Avoid other routed layers over and under MIM structure - if possible. As it is a 4 metal process - and cap-top is connected to M4 there is no threat from top - Now, you might remove passivation dielectric on the top, where there is a MIM - that will reduce field coupling to a very small extent. [effect will not be remarkable]

On the bottom - to reduce decoupling cap value - you might not leave a grounded psub under MIM, to reduce substrate coupling - might draw an NWELL shape under MIM, the NWELL will act virtually as another conducting plate/layer between p-substrate and mim-bot [M3] - and the depletion cap between floating NWell and PSUB - will get added as another cap in series with MIM. [ nothing will improve it dramatically ]

If you get to know some other technique - I am interested to learn.

Thanks

 

[hacksgen]

mim cap umc

Thanks for your advice. I am still trying to figure out measn to suppress the parasitic . From the foundry documents i got to know that the parasitics can be as high as 12 percent of the intended capcitance between bottom plate and subtrate. Hence I have to try to reduce it somehow or cancel out its effect.

 

[deepak242003]

mimcap nwell

you can add nwell that will act as local substrate for cap.... Moreover it will also reduce substrate noise coupling

 

[timof]

I am not sure if parasitic capacitance to ground is that critical in SAR ADC.

What's important is proper capacctance weighting (1:2:4:8...), which can be easily distorted by parasitic coupling to routing nets. So, routing of the bottom plate using lower metal layers (m1, m2) might help.

Also, if the unit capacitance is small (you have to fit the ADC into the pixel pitch), the fringe capacitance between the plates may get redistributed into surrounding routing nets...