Hi There,
I'm designing CMOS buck converter. I'm trying to reduce inductor ripple. But as I design in Hspice, It can't reach between 20-40 percent of average current load. Could you possibly tell me What I can do?
Thanks in advance;
Ebi
Integrated current mode control, using senseFET type
schemes, wants a lot of ripple to give it a sense-able
edge and reject as much VIN noise as possible. Low
ripple slope makes more trailing edge jitter. But ripple
current does cost you efficiency in the input filter
partuicularly. I think you should quantify how much
ripple current you can stand, and how much minimum
you need, and position yourself accordingly. Right up
against the bare minimum is not a good place to put
your production or your customers.
Hi dick_freebird
I'm designing it for ripple current between 20-40 percent of average output current. I don't want to increase amount of inductor(L=4.7uH). when I simulate in Hspice, I can't achieve to desirable ripple current. In addition, I'm designing open loop current mode buck converter without controll circuit. Is it reasonable that ripple current can be reduced after designing controll circuit and closed loop?
Thanks in advance,
Ebi
Hi There,
I'm designing CMOS buck converter. I'm trying to reduce inductor ripple. But as I design in Hspice, It can't reach between 20-40 percent of average current load. Could you possibly tell me What I can do?
Thanks in advance;
Ebi
In order to reduce inductor ripple, it means you are going further into continuous conduction mode (CCM). You wish to reduce the distance between waveform crest and trough.
To do this, increase frequency. Or, reduce the hysteresis travel.
Hi BradtheRad,
I sweep the switching frequency and find optimize amount of it for specific input voltage and load current. I need to investigate both CCM and DCM mode. And I suppose load current below 0.25 average output current is DCM mode and over than it is CCM mode. I wanna design PWM and PFM mode together.
What is the meaning of the heysteresis travel? How can I reduce it?
Thanks,
Ebi
Hi BradtheRad,
I sweep the switching frequency and find optimize amount of it for specific input voltage and load current. I need to investigate both CCM and DCM mode. And I suppose load current below 0.25 average output current is DCM mode and over than it is CCM mode. I wanna design PWM and PFM mode together.
What is the meaning of the heysteresis travel? How can I reduce it?
Thanks,
Ebi
Hysteresis travel has to do with the high and low points at which a waveform is automatically made to change direction. The automatic part is often performed by an op amp. You adjust the hysteresis action via positive feedback.
I could also have said 'hysteresis range' or 'hysteresis limits' or 'hysteresis setpoints'.
Go to the link below. It is my tutorial simulation of a buck converter. It is animated and interactive. (Your computer needs to have Java installed, in order to run Falstad's simulator Java applet.)
Since Java runs on Macs and pc's, his Java applets are cross-platform. That may be one advantage of programming in Java.
Another advantage of his electronic circuit simulator. It can export a link which contains an entire schematic, which will be loaded into his simulator, and then run on anyone's computer (if they have Java installed).