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For digital design, we hope substate to tie VDD/GND. However, if substate has large resistance, there is an IR-drop from well-tap to device bulk node, which will cause the body-effect and impact on device performance.
if there will be votage drop in substract it may cause latch up or body effect or Drain induced voltage lowering problem.
so it is necessary to keep substract resistance lower to avoid this unwanted effect.
one way to reduce substract resistance is high doping in substract but that way leackage current problem will increase so it is not recomanded.
Another way to do is as many as tapping.
Although i am not sure but some companies uses increamental doping profile in substract to achive this or on Silicon on Insulator i think hiph doping will work as there is not any cause of leackage current as device is on insulator layer.
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