Reduce GCLKs for Spartan-II FPGAs

[djnik1362]

hi

i work with Spartan-II FPGAs.

this chip have 4 GCLKs (Global Clock).
In designing projects , in "Design Summary" it mentioned that
"using 2 of 4 of GCLK" for example.
i think there is some way to reduce this item for better performance.

Is there any idea ?

Thanks.