Oct 12, 2010 #1 D djnik1362 Full Member level 2 Joined Aug 9, 2010 Messages 136 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,298 Location IRAN Activity points 2,374 hi i work with Spartan-II FPGAs. this chip have 4 GCLKs (Global Clock). In designing projects , in "Design Summary" it mentioned that "using 2 of 4 of GCLK" for example. i think there is some way to reduce this item for better performance. Is there any idea ? Thanks.
hi i work with Spartan-II FPGAs. this chip have 4 GCLKs (Global Clock). In designing projects , in "Design Summary" it mentioned that "using 2 of 4 of GCLK" for example. i think there is some way to reduce this item for better performance. Is there any idea ? Thanks.