Red wave signal in MdelSim

[queencythea]

hello, i have this verilog code which is a counter that produces red signal in the waveform. what does this red signal mean? please help

module upcounter(clk,reset,enable,out);
input reset;
input enable;
input clk;
output [3:0]out;
reg [3:0] out;
always @(negedge clk)
begin
if(reset==1'b1)
out <= 4'b0000;
else if(enable==1'b1)
out <= out+1;
end

endmodule




here is my test bench

`timescale 1ns / 1ps
module upcounter_tb;
reg reset;
reg enable;
reg clk;
wire [3:0]out;

upcounter uut (
.reset(reset),
.enable(enable),
.clk(clk),
.out(out)
);

initial begin

reset = 0;
enable = 0;
clk = 0;

#10
reset = 1;
enable = 0;

#10
reset = 0;
enable = 1;

#50
reset = 1;
#10
enable = 0;
#20
enable = 1;
#30
reset = 0;

#400;
$finish;
end

always begin
#10 clk = !clk;
end

endmodule


here is the waveform

 

[mrflibble]

Red signal means the signal has X value, which means it has an unknown value at that point in time.

 

[aquanaut]

queencythea,

As mrflibble said, it is X (unknown value). As I can see in waveform, this is because of improper reset.

Try this tb instead of yours,
`timescale 1ns / 1ps
module upcounter_tb;
reg reset;
reg enable;
reg clk;
wire [3:0]out;

upcounter uut (
.reset(reset),
.enable(enable),
.clk(clk),
.out(out)
);

initial begin

reset = 1;
enable = 0;
clk = 0;

#10
reset = 1;
enable = 0;

#10
reset = 0;
enable = 1;

#50
reset = 1;
#10
enable = 0;
#20
enable = 1;
#30
reset = 0;

#400;
$finish;
end

always begin
#10 clk = !clk;
end

endmodule