Recursive function - System Verilog

[wisemonkey]

Hi,
So I've decided to use SystemVerilog for design.
Now there is a combinational logic which can be implemented with recursive function, And number of function call is constant (precompile parameter)
My question is, As synthesizer/compiler tools know exactly number of instances for that particular logic, Can I use recursive function safely?

Thanks

 

[ljxpjpjljx]

better not to use it with SV!

 

[wisemonkey]

I may not be completely aware of Verilog/SV features so if I'm wrong please correct me.
But as much as I know only SV has recursive and void functions ain't it? And I want to use recursive function cause it makes it possible to code that combinational block