reconfigurable computing

[deepa]

reconfigurable verilog mux

HI,
i am trying to write code to dynamically reconfigure two multiplexers...like there are 2 ,4*1 muxes with which a 8*1 mux is done..when not needed,one 4*1 mux must not come in place..
how do i change my code to make this work..

 

[echo47]

It sounds like you need to feed your two 4-to-1 muxes into a 2-to-1 mux.
If you show us your code, I'm sure someone can help you change it.

 

[deepa]

: reconfigurable computing

well here is my ordinary code of two 4*1 muxes,for a 8*1 mux..

module mux8_to_1(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2,o) ;
input i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2;
output o;
reg o;
reg mux_out1,mux_out2;
MUX4_to_1 m1(i0,i1,i2,i3,s0,s1,mux_out1);
MUX4_to_1 m2(i4,i5,i6,i7,s0,s1,mux_out2);
mux2_to_1 m3(mux_out1,mux_out2,s2,o);
// ### Please start your Verilog code here ###
endmodule

module MUX4_to_1(i0,i1,i2,i3,s0,s1,o) ;


// ### Please start your Verilog code here ###
input i0,i1,i2,i3;
output o;
input s0,s1;
wire d0,d1,d2,d3;
wire o;

assign d0=~s0&~s1&i0;
assign d1=~s0&s1&i1;
assign d2=s0&~s1&i2;
assign d3=s0&s1&i3;
assign o=d0|d1|d2|d3;
endmodule


module mux2_to_1(i0,i1,s,o) ;
input i0,i1,s;
output o;
wire o;
assign o=(i0&~s)|(i1&s);

// ### Please start your Verilog code here ###
endmodule


so now,how do i change my code to make it dynamically reconfigurable.please suggest the corrections

 

[shakeebh]

I had considered the idea of doing reconfigurable computing when deciding my final year project. According to little gatherings I had on the subject is that in order to make an FPGA reconfigure itself, u will have to load fresh configuration bits in the device so as to reshape the connections between various logic components in the device. This can be done by placing a processor/PROM beside and connecting it with the config pins of FPGA. Now when a stimulus would require your device to revamp its setup, the processor or PROM would do the job of loading appropriate configuration data into the FPGA. This way you would be able to do run time reconfiguration.

Your idea of writing a verilog code to reconfigure FPGA is something I am hearing for the first time. Tell me whether some knowlegable person guided you to that or is it ur own musing? I am asking because I want to know if it's really possible

 

[aravind]

yep shakeebh,
what the verilog code written in simple , not the reconfigurable stuffs,
can u just give some example reconfigurable codes then we can learn more. if u have ur course lectures
thanks

 

[shakeebh]

I am sorry aravind I dont have anything on reconfig thing. I am yet to do anything related. However, do share with me if you have any!

 

[deepa]

what can you tell about the xilinx's microblaze..i heard it is used for run time reconfiguration..can you tell me how?

 

[shakeebh]

i dont know about this device. I have however an application note from xilinx describing type of flows for partial reconfiguration of vertex family of devices. You can download it (application note 290) from xilinx website or tell me and I'll upload it here