REASON FOR DIFFERENCE IN PACKAGING

[sita]

HI,

WHAT IS THE PRIMARY BASIS ON WHICH SOME DEVICES PACKAGINGS ARE MADE DIFFERENT?

FOR EG:- IN ORCAD WHILE DURING LAYOUT PHASE WE SEE CAPACITORS AVILABLE IN DIFFERENT PACKAGE SIZES LIKE O5,O3 etc.

IS IT SIMPLY BASED ON SIZE OR SOME OTHER FACTORS IS ALSO CONSIDERED?

THANKS,
SITA

 

[rikie_rizza]

For passive component, size is sometimes related with electrical stress handling capability. Eg, a 100nf capacitor wit voltage range of 10V can be made as small as 1mm in width but that can withstand 400V the width can be around 5mm. Another example is a resistor for small wattage can be as small as 1mm (1/10W) or as big as 25mm for 10W.

In semiconductor, package size are related with wafer size, heat dissipation, customer request, bonding requirement, and so on.

 

[sita]

HI,

THANKS FOR THE REPLY. YOUR ANSWER IS MORE THAN SUFFICIENT FOR MY QUESTION. BUT FOR MY CURIOSITY IN THE TOPIC ,

IS THERE ANY DOCUMENT/ARTICLE ON THE ABOVE TOPIC?

IF YOU KNOW SOMETHING LIKE THAT, CAN YOU PLEASE SHARE IT?

THANKS,
SITA

 

[kender]

IS THERE ANY DOCUMENT/ARTICLE ON THE ABOVE TOPIC?

Hi Sita,

I don't know of such article off-hand.

You can get an insight relatively quickly. Go to DigiKey and pick a datasheet for a falimily of passives. For example, a familiy of capacitors that has multiple voltage ratings and capacitance values and package sizes. Then make a plot of one parameters against another. For example: voltage rating vs. case length or case volume, for the caps with the same capacitance.

If you post your plots here, that would help too, because others will share their insights too.

- Nick

P.S. Please don't use all-capitals. On the web it's equivalent to yelling, and it's considered inpollite.