Real time Eprom emualtor 512kbit x 16bit help...

[badbiki]

74hc590 eprom

has anyone got a circuit design for such an emualtor? i need an emulator that can do up to 512kbit x 16bit in real time...

currently i have a deisng in progress that uses two banks of 1mbit x16bit NV SRAM and switches between banks to edit in 'real time'.

Would anyone be interested in helping me out with this design?

 

[ted]

I think you have the basic consept pretty OK there: Using a SRAM to emulate EPROM is the usual (and a pretty good) way to go. Using NV-SRAM costs some money, but by making your own battery backup you might save some money - but I have not calculated the economy for the alternatives.

As you have stated, by using two RAM chips you can update the one while the other is in "read-mode". Maybe the "real-timeness" of updates issue requires some special switching logic to synchronize the action to the target system, but usually it is not that bad to implement.

So, what is the problem? Why do want to change the arrangement?

Ted

 

[badbiki]

just dont want to have to re-invent the wheel thats all.. if someone has already made a circuit i'd just use that.. if not.. i guess its on to implementing my own

Require a nice fast micro tho.. with plenty of outputs

 

[ted]

I am sorry that I do not have a ready-made design for the circuitry. But this is a relatively simple "wheel" to invent. I would start with suitable RAM chips, either NVRAM or (which I personally would prefer) ordinary SRAM.

To make the basic logic towards the target system should be relatively straight forward, a little depending how fast this emulator must be.

To control and write it all, one may indeed use a microprocessor wth a lot of IO, but maybe that is not necessary--there are other ways to do it:

1) One may use a small amount of logic for building an address register and a data register, which is loaded by the controlling processor. thus reducting the port count very much. Even a tiny PIC would be enough. The logic might be built into a FPGA or CPLD.

2) Simplifying the whole even more, eliminate the processor completely. By using for example PC parallel port one can easily build an interface which is controlled by the PC without any additional processor. This needs some design effort, but by using a FPGA or CPLD the control logic may fit to one neat package, and most design errors may be fixed without a soldering iron.

Good luck,
Ted

 

[badbiki]

Ok, check out this schimatic..

I'll add in 2x 74hc590's for the address line counters (to save I/O's) and wire the data lines over two ports. Then link up the rs232 port and the following switching lines for circuit stuff

-WE ic1
-WE ic2
-Swap Ready (switches all address lines from taget to sram, as switch is only done when OE is High.. possible timing problem so put all address lines accross before switch)
-Direction of reading/writing to sram
-IC1 Select (from micro to chip)
-IC2 Select (same as ^^)
-IC select (for the actualy switch to take place for for taget computer side)

hopefuly the at90s8535 will give me enough I/O's to do all this perfectly i think... then its a matter of programing the damn chip. a Load function, and a Edit specific address function.. and lots of sub routines and lots of serial communication... this part i may need a helping hand with..

 

[badbiki]

yes i get what you are saying.. but i do need to be able to do all this via a serial link Rather not have to design a wild latch network.. can be done yes.. my design here only uses about... wow 20 something ic's.. but thats ok, they are all small a in SOIC format.

i may look for some SRAM controlers to make them like NVsram.. control backup battery etc. or just use some MAXIM DS1234 100ns nvsram..

also have to incorperate a Map tracer into this circuit aswell.. mmm I'll double the data i/o lins are an input for the map tracer no problems.. mmmm