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Reading the status of GPIO when configured for I2C

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Prasad.hegde.sirsi

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Hi,
I would like to implement I2C on GPIO's in Infineon microcontroller. I need a small help.
I am using bit banging technology, while reading the status of the GPIO pin, do I need to make the pin as input and read? (Because there is no GPIO status register).
What will be the status of the pin if previously the pin is configured in output mode and driven to low?

Thanks for your answers, if anyone needs more clarity I would like to write more about this.

Regards
Prasad
 

FvM

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By I2C design, the pin will be only read in open drain state (when it's tri-stated). In other words, it's already set as input.
 

Prasad.hegde.sirsi

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Hi,
Thanks for your inputs, still I am facing issues with this.
Our microcontroller GPIO's are in such a way that both input and output stages can be enabled at the same time.
What I am doing is as follows.
1. Enable both in/out stage.
2. Enable pull up from the AARDWARK reader (which is slave).
3. Send the address byte by bitbanging and write each data bit to the GPIO in OUT register.

Now problem!!
While I am reading the ack from the slave, I read the ack bit from the IN register and clock pulse is generated properly. And this returns me always '1' where as slave has to pull this low for the acknoledge.
I am not able to figure out what is the problem,
whether slave is not able to pull out the SDA to low? or the SDA line is not in the tristate? Am I missing something here?

Thanks in advance for the help
Prasad
 

FvM

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In bit-banging I2C operation, you'll usually drive the pins by the direction register, leaving the output latch in low state. This way, the output changes betweeen output low and tristate. According to I2C standard, both SDA and SCL are operated this way. If none of the involved I2C slaves is performing clock stretching, SCL can be operated push-pull without problems, saving the power for a strong SCL pull-up resistor and speeding up edges.
 

Easyrider83

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If your controller using software i2c in master mode, you can use pull-up and open drain only for SDA line. Slave devices can't drive SCL. So, after you send last bit and waiting acknowledge, you need to reconfigure SDA pin as input and read their status on next SCL pulse.
 

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Slave devices can't drive SCL.
They actually do if implementing clock stretching. It can be often found with microprocessor slaves and other complex peripherals.
 

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