reading file using textio package

[vivo_m]

hello everybody,

i'm trying a simple example to read std_logic_vector from a file and retrieve its equivatent integer value
but there is an error in read() and readline().. actually when i tried to compile textio package i got this error msg
"
# ** Error: (vcom-7) Failed to open design unit file "D:/vhdl projects/vhdl_src/std/textio.vhd" in read mode.
# No such file or directory. (errno = ENOENT)
# C:/modeltech_6.5/win32/vcom failed.
"

any idea how can i overcome this plzzz..


i found that there is an additional library for textio its "standard_textio_additions", i also used it but with same error

any help plzzz



thanks...

 

[TrickyDicky]

you dont need to compile textio, its already included in modelsim.
the standard_textio_additions is a VHDL 1993 version of the VHDL 2008 additions. A newer version of modelsim will support this by default (so you dont need to include it).

 

[vivo_m]

i'm working on version 6.5.. and i actually all of ieee_proposed library packages are not included that's why i added standard_textio_additions
here is my code

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;--conv
USE ieee.std_logic_unsigned.all;
use std.textio.all; 


LIBRARY ieee_proposed;
USE ieee_proposed.standard_textio_additions.all; 
 
entity FILEREAD is
  --generic (stim_file : string  :=  "sim.txt");
  port(
       CLK              : in  std_logic;
       RST              : in  std_logic;
       Y                : out std_logic_vector(4 downto 0);
       X                : out integer;
       EOG              : out std_logic
      );
end FILEREAD;
  
architecture read_from_file of FILEREAD is
----------------------------------------------------------------------------------------------------  
type read_file is file of std_logic_vector(4 downto 0); 
   signal eog_sig :std_logic;
begin
  process (clk)
    file stimulus : read_file open read_mode is "sim.txt";
    variable l: line;
    variable s,Y_sig: std_logic_vector(4 downto 0);
    
    begin
      if (rising_edge(clk)) then
        if rst = '1' then
          EOG_sig <= '0';
          X <= 0;
          Y <= (4 downto 0 =>'0');
        else            
            while not endfile(stimulus) loop
              -- read digital data from input file
              READLINE(stimulus, l);
              READ(l, s);
              Y_sig := s;
              Y<=Y_sig;
              X <= conv_integer(Y_sig);
              --wait until CLK = '1';
            end loop;
            EOG_sig <= '1';
          end if;
          EOG <= eog_sig;
      end if;
    end process;

end architecture;

whenever i compile it it gives me this erroe
"
** Error: D:/vhdl projects/readingValues.vhd(62): No feasible entries for subprogram "readline".
** Error: D:/vhdl projects/readingValues.vhd(63): No feasible entries for subprogram "read".
"


would you plz help me to find where the problem is..

thanks

 

[TrickyDicky]

you need to include ieee_proposed.std_logic_1164.additions.all; for textio with std_logic.

 

[vivo_m]

you need to include ieee_proposed.std_logic_1164.additions.all; for textio with std_logic.

still having the same error about readline()

i though that the problem may be with the file i want to read??
well its .txt containing this data
"00010 00011 11100 10000 00111 11111"
i tried saving it like above and saving it like that
"
00010
00011
11100
10000
00111
11111
"
nothing change still giving me this msg
"No feasible entries for subprogram "readline"."
(
any idea ????

 

[TrickyDicky]

oops, I misread. There is no such thing as a "read_file" type, the file type is "text"

file stimulus : text open read_mode is "sim.txt";

- - - Updated - - -

PS. why dont you upgrade to a more recent version of modelsim, ie. 10.1d? then you dont need the ieee_proposed library (because it has native VHDL 2008 support).

 

[vivo_m]

if so,,, there will be no need to write this line of code
"type read_file is file of std_logic_vector(4 downto 0);" or wt??

well its compiled
but when i started simulating it stopped at "READLINE(stimulus,l)" giving me this msg
"
#** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 600 ns Iteration: 0 Process: /fileread/line__44 File: D:/masters code/vhdl projects/readingValues.vhd
# Fatal error in Process line__44 at D:/masters code/vhdl projects/readingValues.vhd line 63
#
# HDL call sequence:
# Stopped at D:/vhdl projects/readingValues.vhd 63 Process line__44
"
i don't know what to do

would you plz try it for me and tell me whats wrong and how to overcome it plzzz??

thanks

- - - Updated - - -

PS. why dont you upgrade to a more recent version of modelsim, ie. 10.1d? then you dont need the ieee_proposed library (because it has native VHDL 2008 support).

actually i don't have its source :$
i know its an old version but its the only licensed one i've :s

 

[TrickyDicky]

Your file type declaration isnt needed because you're reading std_logic_vectors from a text file. It is only required if you want to read from a data file (and I wouldnt recommend doing that).
A SIGSEGV is usually a modelsim crash. So I would highly suggest upgrading your version of modelsim. You licence should cover all versions. The error doesnt correspond to aa line in the code you posted.

 

[vivo_m]

Thanks alot i will find out an updated source and let you know the updates..
thanks alot TrickyDicky