Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Reading external data-file to Spartan-3E using verilog

Status
Not open for further replies.

MPTSheff

Newbie level 3
Newbie level 3
Joined
Aug 14, 2013
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
47
I'm trying to read in a data file to a spartan 3E starter kit using verilog. The file is simply a list of 8bit binary numbers (eg.11000011). I wish to read each line in one at a time, in order to activate the appropriate LEDs. The code I've written is listed below and uses $fscanf to read in the data. However, when I try to generate the programming file I get the error: "File argument of function $fscanf is not constant."

I am also unsure where exactly to physically place my data file. From the examples I've found eg. "in = $fopen("data.txt","r");" presumably this should be in the same directory as the verilog module file?

Any help would be greatly appreciated.


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
module inputdata(
  output reg [7:0] leds,
  input wire clock,
  input reset
    );
 
  integer in, line;
  reg [47:0] din;
  reg [23:0] state;
  
  initial begin
     in = $fopen("data.txt","r");
  end
  
  always @( posedge clock or negedge reset) begin
    if( reset == 1'b0 ) begin
       state <= 24'b0;       // Allows the change in LEDs to be seen 
        leds <= 8'b0;
    end else begin
       state <= state + 24'b1;
        if( state == 24'hFFFFFE ) begin
          line = $fscanf(in, "%b",din);      // reads in value to be set to LED
        end
        if( state == 24'hFFFFFF ) begin
          leds <= line;                          // sets LED value
        end
     end
  end
 
endmodule

 
Last edited:

$fscanf is not synthesizable. It is used for testbenches or behavioural models.

If you want to transfer data from a PC , you will have to create a hardware interface in the FPGA that can pull data from the PC and software in the PC to send the data to the FPGA. IIRC the Spartan boards have a USB/UART chip that you can use. You would design a UART in Verilog that talks to the USB/UART device amd then use a PC tool like Hyperterminal or TeraTerm to send the FPGA the data. The USB/UART device will look like a COM port to the terminal emulator.

r.b.
 
HI.I want programming synthsizer si4136 with fpga. but I dont know how can I start?the si4136 has three pin for programmig, sclk and SEN and SDATA. IF I DESCRIBE it operation:
when sclk event and sclk=1 and SEN=0 the sdata IS ACTIVE and with edge up sclk=1 a bit of sdata transfer to internal register of si4136.if I want to programming for example reg1 and reg3 and reg6(when is RF operation) .how should I do?
sclk(cycle time)=40ns(minimum)
SEN(PULSE WIDTH)= 10ns(when SEN=1)
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top