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The PC's parallel port electrical characteristics are given in IEEE Std 1284-2000.
It says this about a Level 1 device:
8.3.2.2 Receiver requirements
a) Receivers shall operate at nominal 5 V TTL levels.
b) The receiver high-level input threshold shall not exceed 2.0 V.
c) The receiver low-level input threshold shall be at least 0.8 V.
d) The receiver high-level input sink current shall not exceed 0.32 mA at 2.0 V.
e) The receiver low-level input source current shall not exceed 12 mA at 0.8 V.
f) Pull-up resistors, if present, shall be not less than 470 Ω ± 5% for control and status signals, and not less than 1000 Ω ± 5% for data signals. It is recommended that these minimum values be used. Current supplied by pull-up resistors, if present, shall be included in the input current limits, list items d) and e).
g) Circuit and stray capacitance shall not exceed 50 pF of uncompensated capacitance. Compensation for larger capacitance may be supplied by a pull-up resistor, provided that it meets the requirements of list item f).
h) The maximum rise or fall time is as expected for a 2 m cable, 120 ns as measured between the 0.8 V and 2.0 V levels.
i) The receiver should be able to withstand peak input voltage transients between -2.0 V and 7.0 V without damage or improper operation.
and this about a Level 2 device:
8.3.3.2 Receiver requirements [level 2 device]
a) The receiver shall withstand peak input voltage transients between -2.0 V and 7.0 V without damage or improper operation.
b) The receiver high-level input threshold shall not exceed 2.0 V.
c) The receiver low-level input threshold shall be at least 0.8 V.
d) The receiver shall provide at least 0.2 V input hysteresis. Increasing this hysteresis (up to a maximum of 1.2 V) will improve noise immunity.
e) The receiver high-level input sink current shall not exceed 20 µA at 2.0 V.
f) The receiver low-level input source current shall not exceed 20 µA at 0.8 V.
g) Circuit and stray capacitance shall not exceed 50 pF.
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