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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity s_ram is
port(
rama_clk : in std_logic;
rama_we : in std_logic;
rama_addr : in std_logic_vector(5 downto 0);
rama_din : in std_logic_vector(3 downto 0);
rama_dout : out std_logic_vector(3 downto 0));
end entity s_ram;
architecture syn of s_ram is
type RamType is array(0 to 2) of bit_vector(3 downto 0);
impure function InitRamFromFile (RamFileName : in string) return RamType is
File RamFile : text open READ_MODE is RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType'range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile("c:\ram_init.txt");
begin
process (rama_clk)
begin
if rama_clk'event and rama_clk = '0' then
if rama_we = '1' then
RAM(conv_integer(rama_addr)) <= to_bitvector(rama_din);
end if;
rama_dout <= to_stdlogicvector(RAM(conv_integer(rama_addr)));
end if;
end process;
end syn;
the main code is perfect .. i want the same thing to be done on test bench ..