voho
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Hi all
Configuration is the process of loading a design bitstream into the FPGA internal configuration memory. Readback is the process of reading that data.
If somebody can help me if has always doing this :
The CAPTURE_VIRTEX component is used in the FPGA design to control when the logic
states of all the registers are captured into configuration memory. The CLK pin may be drivenby any clock source that would synchronize Capture to the changing logic states of the
registers.
Thank's regards
Configuration is the process of loading a design bitstream into the FPGA internal configuration memory. Readback is the process of reading that data.
If somebody can help me if has always doing this :
The CAPTURE_VIRTEX component is used in the FPGA design to control when the logic
states of all the registers are captured into configuration memory. The CLK pin may be drivenby any clock source that would synchronize Capture to the changing logic states of the
registers.
Thank's regards