Read file(for data pattern) with negative numbers in any HDL (VHDL/verilog)

[syedshan]

Hi all,


as fasr as I know verilog cannot read negative numbers, but I have no idea of writing test bench from VHDL and
since time constraint I am getting more and more confused as I open each link via google for VHDL read file...

I have data with both negative and positive integer format and am unable to read the data.
I did previously similar thing thru verilog but then it was in binary "0101001" rtc. format...

Now I made the .bin format using matlab but simulator rejected to understand the format.

What to do...

need quick reply if can :roll:

Bests,
Shan

 

[FvM]

Which file format do you refer to? Any HDL can represent negative numbers, in so far it's surely possible for binary files, if you interprete the data as signed numbers. VHDL textio package does support integer and real numbers, both can be negative. I presume, there's a similar option in Verilog, but I didn't use it for testbenches yet.

 

[syedshan]

format is .txt

But I can change it using the matlab to .bin as well.

 

[TrickyDicky]

does $fscanf not read in -ve numbers with %d? (Im a VHDL guy who has dabbled in Verilog/SV)

 

[FvM]

Apparently it does:

d Matches an optionally signed decimal number, consisting of the optional sign from the set + or -,
followed by a sequence of characters from the set 0,1,2,3,4,5,6,7,8,9 and _, or a single value from
the set x,X,z,Z,?.

I would prefer text format and decimal numbers for testbenches.