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read data from UART in FPGA

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rezvania

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Hi, I want to use UART and read data from UART and transmit it as input to my project.

I find UART code and it works. sometimes maybe line be idle and then START bit comes, next 8 bit data comes and then Stop bit comes. I read data by clk with 16 times baud rate and I get data. when 1 cycle is done, a pulse be high. when pulse comes up, I read output. this is routine but I have a problem.

if line be idle for long time I don't have new input for my project and previous data read again as new data. I want to know what do you do in this case? you use FIFO or other things? Thank you for all answers ...
 

rezvania

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No, I say we have two block, a asynchronous(UART) and another is synchronous(FPGA blocks), How do we match these?
 

FvM

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Different question, similar answer. You'll sychronize the data ready pulse to the FPGA clock domain.
 
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