Read and write from test vector file using vhdl

[shiva17]

Hi every one,

I wrote the test bench to read from one text file and write it in another text file in first cycle. Now i need to read the data from the written text file and write the same in the text file which was read before in second cycle. i have to do this for 10 cycles but i'm not able to find the logic for that can any one please help me out in solving this.

Thank you

 

[TrickyDicky]

please can you expand and post more details about what you are trying to do, hopefully with a code example and explain what the problem is.
You cannot have the same file open for reading and writing at the same time. But you can open and close files during simulation.

 

[shiva17]

i have two memory blocks when one memory is reading the data the other one will write the data. I'm using two different file for reading and writing at the same time. In first cycle when one memory block is reading the other will write and the data is stored in text file. In second cycle i should read the data from written text file but I'm not able to do that I'm missing out the logic. i should contineously ready and write the data 10 times you can see the attached snap of my simulated data that is mdata1 and mdata2 in first cycle when oe is 0 it is reading in mdata1 and writing in mdata2. In the second cycle i should read the data which is written in mdata2 i.e when soe2 is 0 but as you can see in snap it is taking as high impedence . i hope this is useful

 

[TrickyDicky]

It doesnt really help, as we cannot see your code.
But why are you storing memory contents in a text file? why not locally in a signal or similar? is this some memory model you have constructed or are you intending to use this for synthesis (reading and writing files is not suitable for hardware)

Please elaborate on what you are actually doing and what you are trying to do, it is still not clear. Please post the code with specific problems.