Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

re : register in input to register path in p & r

Status
Not open for further replies.

jaya sree

Member level 3
Joined
Nov 9, 2009
Messages
55
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
india
Activity points
1,791
Hai everyone

According to my knowledge , input to register path must start at input port and end at data/scan pin of register. however i am seeing one more register in the path. Is this normal? did i miss any constraint. SCLK is the main clock in our design.
The path is going to RESET pin of one register and then going to data pin of register ( endpoint) . The module is scan related.


I have attached the path
 

Attachments

  • doubt - Copy.doc
    13.6 KB · Views: 81

below is path :


Startpoint: TST_TARG_sms_early_resetb
(input port clocked by SCLK)
Endpoint: vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/t_data_2_reg_1_
(rising edge-triggered flip-flop clocked by SCLK)
Path Group: io_to_flop
Path Type: max

Point Fanout Cap Trans Incr Path
----------------------------------------------------------------------------------------------------------------------------------------------
clock SCLK (rise edge) 0.038 0.000 0.000
clock network delay (ideal) 0.000 0.000
input external delay 0.184 0.184 f
TST_TARG_sms_early_resetb (in) 0.000 0.000 0.184 f
TST_TARG_sms_early_resetb (net) 11 0.007
vl_sms_sblk_scb_proc_1_sms_1_stp/rst_sms (sblk_scb_proc_1_stp) 0.000 0.000 0.184 f
vl_sms_sblk_scb_proc_1_sms_1_stp/rst_sms (net)
vl_sms_sblk_scb_proc_1_sms_1_stp/U1/A (hdbfxss2ur) 0.000 0.000 0.184 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U1/Z (hdbfxss2ur) 0.079 0.053 0.237 f
vl_sms_sblk_scb_proc_1_sms_1_stp/n1 (net) 28 0.033
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/rst_sms (sblk_scb_proc_1_bist) 0.000 0.000 0.237 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/rst_sms (net)
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U967/A (hdbfxss2ur) 0.079 0.000 0.237 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U967/Z (hdbfxss2ur) 0.085 0.075 0.311 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n1437 (net) 33 0.035
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U971/A (hdbfxss2ur) 0.085 0.000 0.311 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U971/Z (hdbfxss2ur) 0.088 0.077 0.389 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n1434 (net) 34 0.037
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U972/A (hdbfxss2ur) 0.088 0.000 0.389 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U972/Z (hdbfxss2ur) 0.077 0.072 0.461 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n1433 (net) 29 0.032
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U814/A (hdbfxss2ur) 0.077 0.000 0.461 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U814/Z (hdbfxss2ur) 0.074 0.069 0.530 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n1445 (net) 28 0.031
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U969/A (hdbfxss2ur) 0.074 0.000 0.530 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U969/Z (hdbfxss2ur) 0.084 0.074 0.603 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n1436 (net) 32 0.035
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U834/A (hdbfxss2ur) 0.084 0.000 0.603 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U834/Z (hdbfxss2ur) 0.077 0.072 0.675 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n1438 (net) 28 0.032
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/tbox_r_reg_267_/RESET (hdrmsfqxss1ur) 0.077 0.000 0.675 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/tbox_r_reg_267_/Q (hdrmsfqxss1ur) 0.015 0.039 0.714 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/str_descr[2] (net) 2 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U957/A (hdinxss1ur) 0.015 0.000 0.714 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U957/Z (hdinxss1ur) 0.018 0.016 0.730 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n851 (net) 3 0.002
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U1133/A2 (hdioai22xss1ur) 0.018 0.000 0.730 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U1133/Z (hdioai22xss1ur) 0.025 0.021 0.751 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n933 (net) 2 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U955/B (hdan3xss2ur) 0.025 0.000 0.751 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U955/Z (hdan3xss2ur) 0.016 0.031 0.782 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/n802 (net) 3 0.004
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U952/A (hdnr2xss4ur) 0.016 0.000 0.782 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/U952/Z (hdnr2xss4ur) 0.026 0.018 0.800 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/addr_enb (net) 8 0.007
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_bist/addr_enb (sblk_scb_proc_1_bist) 0.000 0.000 0.800 r
vl_sms_sblk_scb_proc_1_sms_1_stp/addr_enb (net)
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/addr_enb (sblk_scb_proc_1_adg) 0.000 0.000 0.800 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/addr_enb (net)
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U195/A (hdinxss3ur) 0.026 0.000 0.800 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U195/Z (hdinxss3ur) 0.019 0.017 0.817 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n326 (net) 11 0.008
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U193/A (hdnr2xss3ur) 0.019 0.000 0.817 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U193/Z (hdnr2xss3ur) 0.042 0.029 0.846 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n108 (net) 11 0.011
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U190/A (hdinxss2ur) 0.042 0.000 0.846 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U190/Z (hdinxss2ur) 0.028 0.025 0.871 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n106 (net) 9 0.008
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U223/B2 (hdaoi222xss4ur) 0.028 0.000 0.871 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U223/Z (hdaoi222xss4ur) 0.034 0.033 0.904 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n38 (net) 2 0.002
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U174/A (hdinxss1ur) 0.034 0.000 0.904 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U174/Z (hdinxss1ur) 0.020 0.018 0.922 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n62 (net) 3 0.002
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U96/A (hdnd2xss1ur) 0.020 0.000 0.922 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U96/Z (hdnd2xss1ur) 0.022 0.012 0.934 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n60 (net) 1 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U400/A (hdoai211xss1ur) 0.022 0.000 0.934 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U400/Z (hdoai211xss1ur) 0.052 0.038 0.972 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n244 (net) 3 0.003
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U172/A (hdinxss2ur) 0.052 0.000 0.972 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U172/Z (hdinxss2ur) 0.021 0.018 0.989 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n245 (net) 3 0.002
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U169/B (hdxn2xss1ur) 0.021 0.000 0.989 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U169/Z (hdxn2xss1ur) 0.020 0.049 1.038 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n236 (net) 2 0.002
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U168/B (hdxn2xss2ur) 0.020 0.000 1.038 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U168/Z (hdxn2xss2ur) 0.019 0.046 1.085 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n67 (net) 3 0.003
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U165/A (hdinxss2ur) 0.019 0.000 1.085 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U165/Z (hdinxss2ur) 0.012 0.011 1.096 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n124 (net) 3 0.003
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U82/B (hdxn2xss1ur) 0.012 0.000 1.096 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U82/Z (hdxn2xss1ur) 0.019 0.047 1.143 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n126 (net) 2 0.002
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U285/A (hdaoi21xss1ur) 0.019 0.000 1.143 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U285/Z (hdaoi21xss1ur) 0.025 0.010 1.153 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n125 (net) 1 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U286/A (hdaoi311xss1ur) 0.025 0.000 1.153 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U286/Z (hdaoi311xss1ur) 0.037 0.029 1.182 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n127 (net) 1 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U287/A (hdaoi21xss1ur) 0.037 0.000 1.182 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U287/Z (hdaoi21xss1ur) 0.025 0.013 1.195 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n129 (net) 1 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U288/B1 (hdoai21xss1ur) 0.025 0.000 1.195 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U288/Z (hdoai21xss1ur) 0.026 0.021 1.216 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n130 (net) 1 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U80/B (hdnr2xss1ur) 0.026 0.000 1.216 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U80/Z (hdnr2xss1ur) 0.017 0.015 1.232 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n159 (net) 2 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U289/B2 (hdaoi22xss1ur) 0.017 0.000 1.232 f
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U289/Z (hdaoi22xss1ur) 0.028 0.027 1.258 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n132 (net) 2 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U290/B2 (hdiaoi22xss1ur) 0.028 0.000 1.258 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U290/Z (hdiaoi22xss1ur) 0.035 0.033 1.292 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n134 (net) 1 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U79/B1 (hdioai21xss1ur) 0.035 0.000 1.292 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/U79/Z (hdioai21xss1ur) 0.015 0.036 1.328 r
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/n2 (net) 1 0.001
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/t_data_2_reg_1_/D (hdrmsfqxss2ur) 0.015 0.000 1.328 r
data arrival time 1.328

clock SCLK (rise edge) 0.038 1.052 1.052
clock network delay (ideal) 0.000 1.052
clock reconvergence pessimism 0.000 1.052
clock uncertainty -0.100 0.952
vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/t_data_2_reg_1_/CLK (hdrmsfqxss2ur) 0.952 r
library setup time -0.034 0.918
data required time 0.918
----------------------------------------------------------------------------------------------------------------------------------------------
data required time 0.918
data arrival time -1.328
----------------------------------------------------------------------------------------------------------------------------------------------
slack (VIOLATED) -0.409
 

do you have the reset pin properly define inside the liberty (timing) file?
it is like the tool does not stop at the nreset pin.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top