jaya sree
Member level 3
Hai everyone
According to my knowledge , input to register path must start at input port and end at data/scan pin of register. however i am seeing one more register in the path. Is this normal? did i miss any constraint. SCLK is the main clock in our design.
The path is going to RESET pin of one register and then going to data pin of register ( endpoint) . The module is scan related.
I have attached the path
According to my knowledge , input to register path must start at input port and end at data/scan pin of register. however i am seeing one more register in the path. Is this normal? did i miss any constraint. SCLK is the main clock in our design.
The path is going to RESET pin of one register and then going to data pin of register ( endpoint) . The module is scan related.
I have attached the path