Re : help about error in synthesis of my code in xilinx ise

[kakarala]

hi

I am trying to synthesise a code to compute sum of absolute difference between to image blocks, i wrote code but when i synthesise the code it gives me following error.

INTERNAL_ERROR:Xst:cmain.c:3446:1.47 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com

Process "Synthesis" failed


the code is


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.images.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SAD1 is
port ( clk : in std_logic;
rst : in std_logic;
currblk_row : in integer;
currblk_column : integer;
refblk_row : in integer;
refblk_column : in integer;
sad : out integer);
end SAD1;

architecture Behavioral of SAD1 is
signal tmp: integer:=0;
signaL x,y,x1,y1 : integer;
begin

sum_ad : process(clk,rst)

begin
if rst='1' then
sad <= 0;
tmp <= 0;
elsif (clk ='1' and clk'event) then
sad <= 0;
for i in 0 to 3 loop
for j in 0 to 3 loop
x<=(4*currblk_row) + i;
y<=(4*currblk_column) + j;
x1<=(4*refblk_row)+i;
y1<=(4*refblk_column)+j;
tmp <= tmp+ abs(curr_image((x*64)+y)- ref_image((x1*64)+y1));
end loop;
end loop;
sad <= tmp;
end if;
end process;
end Behavioral;

 

[permute]

I'm fairly certain that code also doesn't do what you think.
<= is the "nonblocking assign". what this means is that "tmp" will have 16 nonblocking assigns _listed_ within the evaluation of the process. of this list of 16 assigns ONLY ONE will be evaluated -- the last one. Thus your loops will be removed, and replaced with the i=3, j=3 case (the last case).

Furthermore, the same applies for the interactions between x,y,x1,y1 and tmp. x,y,x1,y1 will not be updated on the same clock cycle as tmp. The evaluations are all done at the same instant, and after all expressions affected by "clk'event" are determined. eg, if another process provides currblk_* in a clocked process, then there are no race conditions. both processes will use the current values to determine the next values. This means one process will not update values used in a second process on the same clk'event (doing such would make process evaluation order important).

In general, if you have async resets then you should either reset all assigned signals or move some to another process (or if clk'event...). This is because, during a reset, x,y,x1,y1 must retain their previous values (even if a clock edge occurs). You haven't given these registers permission to change or given them a value to change to. Giving them a reset solves this, as does moving x,y,x1,y1 into a non-resetable "if clk'event ..." statement.

It is not required to set "sad <= 0;" at the top of the loop, though it doesn't matter for the above reasons. as mentioned, only the last non-blocking assignment to sad will be evaluated.

What is "curr_image"? its not declared in the VHDL.


most likely you will want to think about pipelining the above operations, or using a state machine.