Re-convergence of synchronizers

[keyboardcowboy]

I have 2 similar analog blocks which output a single bit signal. The signal from Block A is not related to the signal from Block B. Before using the signal in my sequential logic, I have synchronized each separately using a 2DFlipFlop synchronizer. CDC checking tools complain that this is a "Re-convergence of synchronizers" problem. How do I get around this?. The analog blocks which generate this signal don't have a clock. It is an async signal. The signal itself is very slow (it rarely changes)

 

[D.A.(Tony)Stewart]

This seems to lack a purpose, has no outputs and needs work.

 

[dick_freebird]

The "complaint" almost sounds like a good thing. No idea what it means.
I'd expect that the manual does.

 

[keyboardcowboy]

This seems to lack a purpose, has no outputs and needs work.

The outputs from the analog block enable a part of digital circuit which is all the way to the right after the FF

 

[FvM]

The problem is that timing analysis is making assuptions about the relation of both signals, that according to your circuit description, don't apply. There's no use of sychronizing the signals separately. Change the processing order, use a pure combinational OR and one synchronizer.

 

[kaz1]

The problem is that timing analysis is making assuptions about the relation of both signals, that according to your circuit description, don't apply. There's no use of sychronizing the signals separately. Change the processing order, use a pure combinational OR and one synchronizer.

That makes sense. The two async inputs can interact at source (ORed) then the single ORed output synced to digital clock. The timing tool has its rule here although user may see that the two signals are semi-static and could work either way.

 

[D.A.(Tony)Stewart]

DRC on CDC can flag errors and false positives when no bandwidth constraints are defined for the signals passing across domains. Convergence errors may occur from this without the handshaking delays known and the input speed defined. You know the input is slow, but is that defined?

 

[keyboardcowboy]

DRC on CDC can flag errors and false positives when no bandwidth constraints are defined for the signals passing across domains. Convergence errors may occur from this without the handshaking delays known and the input speed defined. You know the input is slow, but is that defined?

No, it hasn't been defined. define it as in timing constraints?

 

[D.A.(Tony)Stewart]

https://www.edn.com/solving-the-toughest-problems-in-cdc-analysis/