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During chip manufacturing, the following parameters affect nets RC. Metal width = W, Metal thickness = T, IMD (dielectric) thickness. From wafer to wafer, from chip to chip, even from net to net (on the same chip) all of these parameters can be vary.
The different ratio of these parameters variations will lead to different RC corners:
Re: RC-extractions/coners -> how many should be done for SignOff
Oh...that's right. One more question. Is it compulsory that the RCworst corner should be for W(min) + T(min) + D(min) ?? Suppose, in my design, the capacitance effect is so high compared to resistance of the net. In such a situation, won't it be W(max)+T(max)+D(min)??
Still I won't be having a separate Rbest or Rworst corncer since RCworst will become Rbest now.
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oh..sorry for that question. Then my Cworst, RCworst and Rbest corners corners will become same!!
in 130nm probably less number of corners will do but these are too simplistic equations you are putting. In lower technologies things become too complicated. Cworst ,Rcworst and Rbest don't become the same ever as you will see violations in each of them. The number of IP corners become very high in mobile SOC because of multiple voltage designs. You should try a big design to run these test cases with various extraction to get the appropriate list. But there is always an increase in the number of corners rather than reduction as you go into lower technologies. It is very expensive to generate these libraries.... but that is the nature of problem ;-)